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Data Sheet

AD9655

Figure 64. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths

of Less Than 24 Inches (Approximate 6 Inch Trace Length Result Shown) on

Standard FR-4 Material, External 100 Ω Far-End Termination Only

Figure 65. TIE Jitter Histogram for Trace Lengths Less Than 24 Inches

(Approximate 6 Inch Trace Length Result Shown)

Figure 64 shows an example of the LVDS output data eye using

the ANSI-644 standard (default), and Figure 65 shows a time

interval error (TIE) jitter histogram with trace lengths of less

than 24 inches on standard FR-4 material.

Figure 66 shows an example of the LVDS output data eye using

the ANSI-644 standard (default), and Figure 67 shows a time

interval error (TIE) jitter histogram with trace lengths greater

than 24 inches on standard FR-4 material. Note that the TIE

jitter histogram reflects the decrease of the data eye opening as

the edge deviates from the ideal position. It is the responsibility

of the user to determine if the waveforms meet the timing budget

of the design.

The format of the output data is twos complement by default.

See Table 11 for an example of the output coding format. To

change the output data format to offset binary, see the

Memory Map section.

Data from each ADC is serialized and provided on a separate

channel in two lanes in DDR mode. The data rate for each serial

stream is equal to (16 bits × the sample clock rate)/2 lanes, with

a maximum of 1 Gbps/lane (16 bits × 125 MSPS)/(2 lanes) =

1 Gbps/lane). The minimum conversion rate is 20 MSPS.

Figure 66. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths

Greater Than 24 Inches (Approximate 36 Inch Trace Length Result Shown) on

Standard FR-4 Material, External 100 Ω Far-End Termination Only

Figure 67. TIE Jitter Histogram for Trace Lengths Greater Than 24 Inches

(Approximate 36 Inch Trace Length Result Shown)

Two output clocks assist in capturing data from the AD9655.

The DCO clocks the output data and is equal to 4× the sample

clock (CLK) rate for the default mode of operation. Data is

clocked out of the AD9655 and must be captured on the rising

and falling edges of the DCO that supports DDR capturing. The

FCO signals the start of a new output byte and is equal to the

sample clock rate in 1× frame mode. See the Timing Diagrams

section for more information.

When the SPI is used, the DCO phase can be adjusted in

approximately 60° increments relative to one data cycle (30°

relative to one DCO cycle). This allows the user to refine system

timing margins if required. The example DCO+ and DCO−

timing, as shown in Figure 2, is 180° relative to one data cycle

(90° relative to one DCO cycle).

In default mode, as shown in Figure 2, the MSB is first in the

data output serial stream. This can be inverted by using the SPI

so that the LSB is first in the data output serial stream.

Rev. 0 | Page 25 of 37

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