AD9655 datasheet(37/38 Pages) AD

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AD9655

Data Sheet

Rev. 0 | Page 36 of 37

APPLICATIONS INFORMATION

DESIGN GUIDELINES

Before starting design and layout of the AD9655 as a system, it

is recommended that the designer become familiar with these

guidelines, which describe the special circuit connections and

layout requirements needed for certain pins.

POWER AND GROUND GUIDELINES

When connecting power to the AD9655, it is recommended

that two separate 1.8 V supplies be used. Use one supply for

analog (AVDD); use a separate supply for the digital outputs

(DRVDD). For both AVDD and DRVDD, use several different

bypass capacitor values to cover both high and low frequencies.

Place these capacitors close to the point of entry at the PCB

level and close to the pins of the device, with minimal trace length.

A single PCB ground plane is sufficient when using the

AD9655. With proper bypassing and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance

is easily achieved.

CLOCK STABILITY CONSIDERATIONS

When powered on, the AD9655 enters an initialization phase

during which an internal state machine sets up the biases and

the registers for proper operation. During the initialization

process, the AD9655 needs a stable clock. If the ADC clock

source is not present or not stable during ADC power-up, it

disrupts the state machine and causes the ADC to start up in an

unknown state. To correct this, reinvoke an initialization

sequence after the ADC clock is stable by issuing a digital reset

via Register 0x08. In the default configuration (internal VREF, ac-

coupled input) where VREF and VCM are supplied by the ADC, a

stable clock during power-up is sufficient. WhenVCM is supplied

by an external source, this, too, must be stable at power-up;

otherwise, a subsequent digital reset via Register 0x08 is

needed. Clock instability during normal operation may also

necessitate digital reset to restore proper operation.

The pseudo code sequence for a digital reset is as follows:

SPI_Write (0x08, 0x03)—digital reset.

SPI_Write (0x08, 0x00)—normal operation.

EXPOSED PAD THERMAL HEAT SLUG

RECOMMENDATIONS

It is required that the exposed pad on the underside of the ADC be

connected to analog ground (AGND) to achieve the best electrical

and thermal performance of the AD9655. It is recommended

that an exposed continuous copper plane on the PCB mate to

the AD9655 exposed pad, Pin 0. It is also recommended that

this copper plane have several vias to achieve the lowest possible

resistive thermal path for heat dissipation to flow through the

bottom of the PCB. Solder-fill or plug these vias.

To maximize the coverage and adhesion between the ADC and

PCB, partition the continuous copper plane by overlaying a

silkscreen or solder mask on the PCB into several uniform sections.

This provides several tie points between the ADC and PCB

during the reflow process, whereas using one continuous plane

with no partitions only guarantees one tie point. See Figure 69

for a PCB layout example. For detailed information on

packaging and the PCB layout of chip scale packages, see the

AN-772 Application Note, A Design and Manufacturing Guide

for the Lead Frame Chip Scale Package (LFCSP).

SILKSCREEN PARTITION

PIN 1 INDICATOR

Figure 69. Typical PCB Layout

VCM

Bypass the VCM pin to ground with a 0.1 μF capacitor.

REFERENCE BYPASSING

Externally bypass the VREF pin to ground with a low ESR,

1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic

capacitor.

SPI PORT

The SPI port must not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK, CSB, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,

it may be necessary to provide buffers between this bus and the

AD9655 to prevent these signals from transitioning at the

converter inputs during critical sampling periods.

AD9655 Datasheet(PDF) 37 Page - Analog Devices

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