AD9655

Data Sheet

SWITCHING SPECIFICATIONS

AVDD = 1.8 V and DRVDD = 1.8 V, unless otherwise noted.

Table 6.

Temperature

Min

Typ

Max

Unit

Input Clock Rate

Full

20

1000

MHz

Conversion Rate

Full

20

125

MSPS

Full

4.00

ns

Full

4.00

ns

Full

ns

Full

170

ps

Full

160

ps

Full

ns

Full

ns

Full

ps

Full

ps

Data to Data Skew

Full

±37

±80

ps

Wake-Up Time (Standby)

25°C

250

ns

25°C

250

ms

Pipeline Latency

Full

16

Clock cycles

APERTURE

25°C

1

ns

25°C

80

fs rms

Out-of-Range Recovery Time

25°C

1

Clock cycles

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Measured on standard FR-4 material.

3

The Output parameters can be adjusted via the SPI. The conversion rate is the clock rate after the divider. Valid for 2-lane operation.

4

5

This term does not appear in the Timing Diagrams section, which includes Figure 2 and Figure 3.

6

7

8

Wake-up time from power-down is defined as the time required to return to normal operation from SPI power-down mode. The value of 250 ms assumes a sample

9

TIMING SPECIFICATIONS

Table 7.

Parameter

Description

Limit

Unit

SPI TIMING REQUIREMENTS

See Figure 68, unless otherwise noted

Setup time between the data and the rising edge of SCLK

4

ns min

Hold time between the data and the rising edge of SCLK

2

ns min

Period of the SCLK

40

ns min

Setup time between CSB and SCLK

2

ns min

Hold time between CSB and SCLK

2

ns min

SCLK pulse width high

10

ns min

SCLK pulse width low

10

ns min

Time required for the SDIO pin to switch from an input to an output relative to the

SCLK falling edge

10

ns min

Time required for the SDIO pin to switch from an output to an input relative to the

SCLK rising edge

10

ns min

1

This parameter is not shown in Figure 68.

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