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Data Sheet

AD9655

Output Phase (Register 0x16)

Bit 7—Open

Bits[6:4]—Input Clock Phase Adjust

When the clock divider (Register 0x0B) is used, the applied

clock is at a higher frequency than the internal sampling clock.

Bits[6:4] determine at which phase of the external clock sampling

occurs. This is applicable only when the clock divider is used.

Selecting a value for Bits[6:4] greater than Register 0x0B,

Bits[2:0] is prohibited. See Table 20 for details.

Table 20. Input Clock Phase Adjust Options

Input Clock Phase Adjust,

Bits[6:4]

Number of Input Clock Cycles

of Phase Delay

000 (Default)

001

010

011

100

101

110

111

Bits[3:0]—Output Clock Phase Adjust

See Table 21 for details.

Table 21. Output Clock Phase Adjust Options

Output Clock (DCO),

Phase Adjust, Bits[3:0]

DCO Phase Adjustment

(Approximate Degrees Relative to

the D0x±/D1x± Edge)

0000

0001

0010

120

0011 (Default)

180

0100

240

0101

300

0110

360

0111

420

1000

480

1001

540

1010

600

1011 through 1111

660

Serial Output Data Control (Register 0x21)

The serial output data control register to programs the AD9655

in various output data modes, depending on the data capture

solution. Table 22 describes the various serialization options

available in the AD9655. Note that, in single data rate (SDR)

mode, the DCO frequency is double that of the frequency in

DDR mode for a given sample rate. In SDR mode, to stay within

the capability of the DCO LVDS driver, the ADC sample rate

must be reduced to ≤62.5 MSPS to keep the DCO frequency at

≤500 MHz.

User I/O Control 2 (Register 0x101)

Bits[7:1]—Open

Bit 0—Disable SDIO Pull-Down

Bit 0 can be set to disable the internal 31 kΩ pull-down resistor

on the SDIO/PWDN pin, which limits the loading when many

devices are connected to the SPI bus.

User I/O Control 3 (Register 0x102)

Bits[7:4]—Open

Bit 3—VCM Power-Down

Bit 3 can be set high to power down the internal VCM generator.

This feature is used when applying an external reference.

Bits[2:0]—000

Clock Monitor Control (Register 0x112)

Bit 7—Open

Bit 6—0 (Reserved)

Bits[5:3]—Recovery Mode

By default (Bits[5:3] = 000), recovery mode is off. In this condition,

the AD9655 does not automatically recover from a state change or

corruption due to a clock glitch or irregularity. With recovery mode

off, a digital reset (Register 0x08 = 0x03, then Register 0x08 = 0x00)

is needed to restore the AD9655 to proper operation in case of

disruption due to clock instability.

With clock recovery mode on (Bits[5:3] = 101), AD9655

automatically recovers from corruption due to a clock glitch or

irregularity. After the corruption is autodetected, 31 × 106 clock

cycles are needed to restore proper operation.

Bits[2:0]— Recovery Mode Setup

Recovery mode is set up for correct operation by default

(Bits[2:0] = 111).

VREF Control (Register 0x114)

This register adjusts the internal analog VREF value. A digital reset

using Register 0x08 must follow any change in analog VREF.

Table 22. SPI Register 0x21 Options

Serialization Options Selected

Contents

Serial Output Number

of Bits (SONB)

Frame Mode

Serial Data Mode

DCO Multiplier

Timing Diagram

0x30

16-bit

1×

DDR two-lane bytewise

4 × fS

See Figure 2 (default setting)

0x20

16-bit

1×

DDR two-lane bitwise

4 × fS

See Figure 2

0x10

16-bit

1×

SDR two-lane bytewise

8 × fS

See Figure 2

0x00

16-bit

1×

SDR two-lane bitwise

8 × fS

See Figure 2

0x40

16-bit

1×

DDR one-lane wordwise

8 × fS

See Figure 3

Rev. 0 | Page 35 of 37

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