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AD9655

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 8.

Parameter

Rating

Electrical

AVDD to AGND

−0.3 V to +2.0 V

DRVDD to AGND

−0.3 V to +2.0 V

Digital Outputs (D0x±, D1x±, DCO±,

FCO±) to AGND

−0.3 V to +2.0 V

CLK+, CLK− to AGND

−0.3 V to +2.0 V

VINx+, VINx− to AGND

−0.3 V to +2.0 V

SCLK/DFS, SDIO/PDWN, CSB to AGND

−0.3 V to +2.0 V

RBIAS to AGND

−0.3 V to +2.0 V

VREF to AGND

−0.3 V to +2.0 V

VCM to AGND

−0.3 V to +2.0 V

Environmental

Operating Temperature Range (Ambient)

−40°C to +85°C

Maximum Junction Temperature

150°C

Lead Temperature (Soldering, 10 sec)

300°C

Storage Temperature Range (Ambient)

−65°C to +150°C

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL RESISTANCE

The exposed pad is the only ground connection for the chip.

The exposed pad must be soldered to the AGND plane of the

circuit board. Soldering the exposed pad to the board also

increases the reliability of the solder joints and maximizes the

thermal capability of the package.

Table 9. Thermal Resistance

Package Type

Airflow

Velocity

(m/sec)

θJA1,2

θJC1,3

θJB1,4

ΨJT1,2

Unit

32-Lead LFCSP,

5 mm × 5 mm

37.1

3.1

20.7

0.3

°C/W

1.0

32.4

N/A5

0.5

°C/W

2.5

29.1

N/A5

0.8

°C/W

Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

Per MIL-Std 883, Method 1012.1.

Per JEDEC JESD51-8 (still air).

N/A means not applicable.

Typical θJA is specified for a 4-layer printed circuit board (PCB)

with a solid ground plane. As shown in Table 9, airflow improves

heat dissipation, which reduces θJA. In addition, metal in direct

contact with the package leads from metal traces, through holes,

ground, and power planes reduces θJA.

ESD CAUTION

Rev. 0 | Page 10 of 37

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