AD9655 datasheet(28/38 Pages) AD

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Data Sheet

AD9655

There are 12 digital output test pattern options available that

can be initiated through the SPI. This is a useful feature when

validating receiver capture and timing. See Table 12 for the

available output bit sequencing options. Some test patterns have

two serial sequential words and can be alternated in various

ways, depending on the test pattern chosen.

Note that some patterns do not adhere to the data format select

option. In addition, custom user defined test patterns can be

assigned in Register 0x19, Register 0x1A, Register 0x1B, and

The pseudorandom number (PN) sequence short pattern

produces a pseudorandom bit sequence that repeats itself every

29 − 1 or 511 bits. A description of the PN sequence and how it

is generated can be found in Section 5.1 of the ITU-T 0.150

(05/96) standard. The seed value is all 1s (see Table 13 for the

initial values). The output is a parallel representation of the

serial PN9 sequence in MSB first format. The first output word

is the first 16 bits of the PN9 sequence in MSB aligned form.

Table 13. PN Sequence

Sequence

Initial

Value

Next Three Output Samples

(MSB First), Twos Complement

PN Sequence Short

0x7F83

0x5F17, 0xB209, 0xCED1

PN Sequence Long

0x7FFF

0x7E00, 0x807C, 0x801F

The PN sequence long pattern produces a pseudorandom bit

sequence that repeats itself every 223 − 1 or 8,388,607 bits. A

description of the PN sequence and how it is generated can be

found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The

seed value is all 1s (see Table 13 for the initial values) and the

AD9655 inverts the bit stream in relation to the ITU standard.

The output is a parallel representation of the serial PN23

sequence in MSB first format. The first output word is the first

16 bits of the PN23 sequence in MSB aligned form.

See the Memory Map section for information on how to change

these additional digital output timing features through the SPI.

SDIO/PDWN Pin

For applications that do not require SPI mode operation, the

CSB pin is tied to DRVDD, and the SDIO/PDWN pin controls

the power-down mode according to Table 14.

Table 14. Power-Down Mode Pin Settings

SDIO/PDWN Pin Voltage

Device Mode

AGND (Default)

Run device, normal operation

DRVDD

Power down device

SCLK/DFS Pin

The SCLK/DFS pin is used for output format selection in

applications that do not require SPI mode operation. This pin

determines the digital output format when the CSB pin is held high

during device power-up. When SCLK/DFS is tied to DRVDD, the

ADC output format is twos complement; when SCLK/DFS is

tied to AGND, the ADC output format is offset binary.

Table 15. Digital Output Format

SCLK/DFS Voltage

Output Format

AGND

Offset binary

DRVDD

Twos complement

CSB Pin

Tie the CSB pin to DRVDD for applications that do not require

SPI mode operation. By tying CSB high, all SCLK and SDIO

information is ignored.

RBIAS Pin

To set the internal core bias current of the ADC, place a

10.0 kΩ, 1% tolerance resistor to ground at the RBIAS pin.

OUTPUT TEST MODES

The output test options are described in Table 12 and are

controlled by the output test mode bits at Register 0x0D. When

an output test mode is enabled, the analog section of the ADC is

disconnected from the digital back-end blocks and the test

pattern is run through the output formatting block. Some of the

test patterns are subject to output formatting, and some are not.

The PN generators from the PN sequence tests can be reset by

setting Bit 4 or Bit 5 of Register 0x0D. These tests can be

performed with or without an analog signal (if present, the

analog signal is ignored), but they do require an encode clock.

For general information, see the AN-877 Application Note,

Interfacing to High Speed ADCs via SPI.

Rev. 0 | Page 27 of 37

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