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Data Sheet

AD9655

HARDWARE INTERFACE

The pins described in Table 16 comprise the physical interface

between the user programming device and the serial port of the

AD9655. The SCLK/DFS pin and the CSB pin function as inputs

when using the SPI interface. The SDIO/PDWN pin is bidirec-

tional, functioning as an input during write phases and as an

output during readback.

The SPI interface is flexible enough to be controlled by either

FPGAs or microcontrollers. One method for SPI configuration

is described in detail in the AN-812 Application Note, Micro-

controller-Based Serial Port Interface (SPI) Boot Circuit.

It is recommended that the SPI port not be active during

periods when the full dynamic performance of the converter is

required. Because the SCLK/DFS signal, the CSB signal, and the

SDIO/PDWN signal are typically asynchronous to the ADC clock,

noise from these signals can degrade converter performance. If the

on-board SPI bus is used for other devices, it may be necessary to

provide buffers between this bus and the AD9655 to prevent these

signals from transitioning at the converter inputs during critical

sampling periods.

The SCLK/DFS and SDIO/PDWN pins serve a dual function

when the SPI interface is not in use. When the pins are strapped

to DRVDD or ground during device power-on, they are

associated with a specific function. Table 14 and Table 15

describe the strappable functions supported on the AD9655.

CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers,

the SCLK/DFS pin and the SDIO/PDWN pin serve as standalone

CMOS-compatible control pins. When the device is powered

up, it is assumed that the user intends to use the pins as static

control lines for the output data format and power-down

feature control. In this mode, connect CSB to DRVDD, which

disables the serial port interface.

SPI ACCESSIBLE FEATURES

Table 17 provides a brief description of the general features

accessible via the SPI. These features are described in general in

the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI. The AD9655 device-specific features are described in

detail following Table 18, the external memory map register table.

Table 17. Features Accessible Using the SPI

Feature Name

Description

Power Mode

Allows the user to set either power-down

mode or standby mode

Clock

Allows the user to access the DCS, set the

clock divider, and set the clock divider phase

Offset

Allows the user to digitally adjust the converter

offset

Test I/O

Allows the user to set test modes to have

known data on output bits

Output Mode

Allows the user to set the output mode

Output Phase

Allows the user to set the output clock polarity

ADC Resolution

Allows power consumption scaling with

respect to sample rate

Rev. 0 | Page 29 of 37

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