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AD9655

Data Sheet

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table (see Table 18) has

eight bit locations. The memory map is roughly divided into

three sections: the chip configuration registers (Address 0x00 to

Address 0x02); the device index register (Address 0x05); and the

global ADC function registers, including setup, control, and test

registers (Address 0x08 and beyond).

The memory map register table lists the default hexadecimal

value for each hexadecimal address shown. The column with

the heading Bit 7 (MSB) contains the most significant bit of the

default hexadecimal value given. For example, Address 0x05,

the device index register, has a hexadecimal default value of

0x33. This means that in Address 0x05, Bits[7:6] = 00, Bits[5:4]

= 11, Bits[3:2] = 00, and Bits[1:0] = 11 (in binary). This setting

is the default channel index setting. The default value results in

both ADC channels receiving the next write command. For

more information on this function and others, see the AN-877

Application Note, Interfacing to High Speed ADCs via SPI. This

application note documents the functions controlled by

the AD9655 are documented in the Memory Map Register

Descriptions section.

Open Locations

All address and bit locations not included in Table 18 are not

currently supported for this device. Write unused bits of a valid

address location with 0s. Writing to these locations is required

only when part of an address location is open (for example,

Address 0x05). If the entire address location is open or not listed

in Table 18 (for example, Address 0x13), this address location must

not be written.

Default Values

After the AD9655 is soft reset by Register 0x00, critical registers

are loaded with default values. The default values for the

registers are given in the memory map register table, Table 18.

Logic Levels

An explanation of logic level terminology is as follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Channel Specific Registers

Some channel setup functions can be programmed individually

for each channel. In these cases, channel address locations are

internally duplicated for each channel. These registers and bits

are designated in Table 18 as local. These local registers and bits

can be accessed by setting the appropriate data channel bits

(Channel A or Channel B) and the clock channel DCO bit (Bit 5)

and clock channel FCO bit (Bit 4) in Register 0x05. If all the bits

are set, the subsequent write affects the registers of both channels

and the DCO/FCO clock channels. In a read cycle, only set one

channel (Channel A or Channel B) to read one of the two registers.

If all the bits are set during an SPI read cycle, the device returns the

value for Channel A. Registers and bits that are designated as global

in Table 18 affect the entire device and channel features for which

independent settings are not allowed between channels. The set-

tings in Register 0x05 do not affect the global registers and bits.

Rev. 0 | Page 30 of 37

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