AD9655 datasheet(12/38 Pages) AD

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Data Sheet

AD9655

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

24 AVDD

23 RBIAS

22 VCM

21 VREF

20 CSB

19 DRVDD

18 D0A+

17 D0A–

AVDD

CLK+

CLK–

SDIO/PDWN

SCLK/DFS

DRVDD

D1B–

D1B+

AD9655

TOP VIEW

(Not to Scale)

NOTES

1. THE EXPOSED PAD IS THE ONLY GROUND CONNECTION

ON THE CHIP. IT MUST BE SOLDERED TO THE ANALOG GROUND

OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND HEAT

DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.

Figure 4. Pin Configuration, Top View

Table 10. Pin Function Descriptions

Pin No.

Mnemonic

Description

0, Exposed Pad

AGND,

Exposed Pad

Exposed Pad. The exposed pad is the only ground connection on the chip. It must be soldered to the

analog ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical

strength benefits.

1, 24, 25, 28, 29, 32

AVDD

1.8 V Supply Pins for the ADC Core Domain.

2, 3

CLK+, CLK−

Differential Encode Clock. These pins are PECL-, LVDS-, or 1.8 V CMOS-compatible inputs.

SDIO/PDWN

SPI Data Input/Output (SDIO). This pin is a bidirectional SPI data input/output with a 31 kΩ internal

pull-down resistor.

Non-SPI Mode Power-Down (PDWN). This pin provides static control of chip power-down, and has a 31 kΩ

internal pull-down resistor.

SCLK/DFS

SPI Clock Input in SPI Mode (SCLK). This pin has a 30 kΩ internal pull-down resistor.

Non-SPI Mode Data Format Select (DFS). This provides static control of the data output format. This

pin has a 30 kΩ internal pull-down resistor. Pull DFS high for a twos complement output; pull DFS

low for an offset binary output.

6, 19

DRVDD

1.8 V Supply Pins for Output Driver Domain.

7, 8

D1B−, D1B+

Channel B Lane 1 Digital Outputs.

9, 10

D0B−, D0B+

Channel B Lane 0 Digital Outputs.

11, 12

DCO−, DCO+

Data Clock Outputs.

13, 14

FCO−, FCO+

Frame Clock Outputs.

15, 16

D1A−, D1A+

Channel A Lane 1 Digital Outputs.

17, 18

D0A−, D0A+

Channel A Lane 0 Digital Outputs.

CSB

SPI Chip Select. Active low enable; this pin has a 15 kΩ internal pull-up resistor.

VREF

1.0 V to 1.4 V Voltage Reference Output. Bypass this pin to ground with a 1.0 µF capacitor in parallel

with a 0.1 µF capacitor; this pin internally provides reference voltage to the ADC. This pin can be

disabled via Register 0x114 if external VREF is desired.

VCM

Analog Output Voltage at Mid AVDD Supply. Bypass this pin to ground with a 0.1 µF capacitor; this

pin can be used to set the common mode of the analog inputs externally.

RBIAS

Sets Analog Current Bias. Connect this pin to a 10.0 kΩ (1% tolerance) resistor to ground.

26, 27

VINA−, VINA+

Channel A ADC Analog Inputs.

30, 31

VINB+, VINB−

Channel B ADC Analog Inputs.

Rev. 0 | Page 11 of 37

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