AD9655 datasheet(24/38 Pages) AD

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Data Sheet

AD9655

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals and, as a result, may be sensitive

to the clock duty cycle. Commonly, a ±5% tolerance is required

on the clock duty cycle to maintain dynamic performance

characteristics.

The AD9655 contains a duty cycle stabilizer (DCS) that retimes

the nonsampling (falling) edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows the user to

provide a wide range of clock input duty cycles without affecting

the performance of the AD9655. Noise and distortion performance

are nearly flat for a wide range of duty cycles with the DCS on.

Jitter in the rising edge of the clock is still of concern and is not

easily reduced by the internal stabilization circuit. The duty

cycle control loop does not function for clock rates of less than

20 MHz, nominally. The loop has a time constant associated

with it that must be considered in applications in which the

clock rate can change dynamically. A wait time of 1.5 µs to 5 µs

is required after a dynamic clock frequency increase or decrease

before the DCS loop is relocked to the input signal.

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The following equation shows how SNR

degrades at a given input frequency (fA) due only to aperture

jitter (tJ):

SNR Degradation = 20 log10













A t

In this equation, the rms aperture jitter represents the root sum

square of all jitter sources, including the clock input, analog

input signal, and ADC aperture jitter specifications. IF under-

sampling applications are particularly sensitive to jitter. The

effect of jitter alone on SNR, with no other noise contributors,

is shown in Figure 60.

100

ANALOG INPUT FREQUENCY (MHz)

1000

16 BITS

14 BITS

12 BITS

100

110

120

130

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

10 BITS

8 BITS

RMS CLOCK JITTER REQUIREMENT

Figure 60. Ideal SNR vs. Analog Input Frequency and Jitter

Treat the clock input as an analog signal when aperture jitter

may affect the dynamic range of the AD9655. Separate clock

driver power supplies from the ADC output driver supplies to

avoid modulating the clock signal with digital noise. Low jitter,

crystal controlled oscillators are the best clock sources. If the

clock is generated from another type of source (by gating,

dividing, or other methods), it is recommended that the clock

be retimed by the original clock as the last step.

See the AN-501 Application Note and the AN-756 Application

Note for more information about jitter performance as it relates

to ADCs.

POWER DISSIPATION AND POWER-DOWN MODE

As shown in Figure 61, the power dissipated by the AD9655 is

proportional to its sample rate. The AD9655 is placed in power-

down mode either by the SPI port or by asserting the SDIO/

PDWN pin high when in non-SPI mode. In this state, the ADC

typically dissipates 2 mW. During power-down, the output drivers

are placed in a high impedance state. In non-SPI mode, asserting

the SDIO/PDWN pin low returns the AD9655 to its normal

operating mode. Note that SDIO/PDWN is referenced to the

digital output driver supply (DRVDD) and must not exceed that

supply voltage.

0.16

0.18

0.20

0.22

0.24

0.26

0.28

0.30

0.32

100

120

SAMPLE RATE (MSPS)

VREF = 1.4V

VREF = 1.0V

Figure 61. Total Power Dissipation vs. Sample Rate (fSAMPLE) for fIN = 9.7 MHz,

VREF = 1.0 V and VREF = 1.4 V

The AD9655 achieves low power dissipation in power-down

mode by shutting down the reference, reference buffer, biasing

networks, and clock. When using the SPI port interface, the

user can place the ADC in power-down mode or standby mode.

Standby mode allows the user to keep the internal reference

circuitry powered when faster wake-up times are required. Do

not invoke standby mode while foreground calibration is in

progress. Foreground calibration is invoked automatically at

power-up, and by executing a digital reset with Register 0x08.

Completion is indicated by the contents of Register 0x107 =

0x00. See the Memory Map section for more details on using

these features.

Rev. 0 | Page 23 of 37

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