AD9655 datasheet(20/38 Pages) AD

20 / 38 page

Data Sheet

AD9655

Rev. 0 | Page 19 of 37

THEORY OF OPERATION

The AD9655 is a multistage, pipelined ADC. Each stage

provides sufficient overlap to correct for flash errors in the

preceding stage. The quantized outputs from each stage are

combined into a final 16-bit result in the digital correction

logic. The serializer transmits this converted data in a 16-bit

output. The pipelined architecture permits the first stage to

operate with a new input sample while the remaining stages

operate with preceding samples. Sampling occurs on the rising

edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched capacitor DAC

and an interstage residue amplifier, for example, a multiplying

digital-to-analog converter (MDAC). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy in each stage facilitates digital correction of flash

errors. The last stage consists of a flash ADC.

The output staging block aligns the data, corrects errors, and

passes the data to the output buffers. Then, the data is serialized

and aligned to the frame and data clocks.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9655 is a differential switched

capacitor circuit designed for processing differential input

signals. This circuit can support a wide common-mode range

while maintaining excellent performance. By using an input

common-mode voltage of midsupply, users can minimize signal

dependent errors and achieve optimum performance.

CPAR

CSAMPLE

CPAR

VINx–

VINx+

Figure 45. Switched Capacitor Input Circuit

The clock signal alternately switches the input circuit between

sample mode and hold mode (see Figure 45). When the input

circuit switches to sample mode, the signal source must be

capable of charging the sample capacitors and settling within

one half of a clock cycle.

A small resistor in series with each input can help reduce the

peak transient current injected from the output stage of the

driving source. A differential capacitor, two single-ended

capacitors, or a combination of these capacitors can be placed

on the inputs to provide a matching passive network. This

ultimately creates a low-pass filter at the input to limit unwanted

broadband noise. See the AN-742 Application Note, the AN-827

Application Note, and the Analog Dialogue article “Transformer-

Coupled Front-End for Wideband A/D Converters” (Volume 39,

April 2005) for more information. In general, the precise values

depend on the application.

Input Common Mode

The AD9655 analog inputs are not internally dc-biased.

Therefore, in ac-coupled applications, the user must provide

this bias externally. Setting the device so that VCM = AVDD/2 is

recommended for optimum performance, but the device can

function over a wider range with reasonable performance, as

shown in Figure 46 and Figure 47.

100

1.0

1.1

1.2

0.5

0.6

0.7

0.8

0.9

VCM (V)

SFDR (dBc)

SNR (dBFS)

Figure 46. SNR, SFDR vs. Input Common-Mode Voltage (VCM), fIN = 9.7 MHz,

fSAMPLE = 125 MSPS, VREF = 1.0 V

100

0.95

1.00

0.70

0.75

0.80

0.85

0.90

VCM (V)

SFDR (dBc)

SNR (dBFS)

Figure 47. SNR, SFDR vs. Input Common-Mode Voltage (VCM), fIN = 9.7 MHz,

fSAMPLE = 125 MSPS, VREF = 1.4 V

AD9655 Datasheet(PDF) 20 Page - Analog Devices

AD9655 Datasheet(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL