AD9655 datasheet(25/38 Pages) AD

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AD9655

Data Sheet

DIGITAL OUTPUTS AND TIMING

The AD9655 differential outputs conform to the ANSI-644

LVDS standard on default power-up. This default setting can be

changed to a low power, reduced signal option (similar to the

IEEE 1596.3 standard) via the SPI. The LVDS driver current is

derived on chip and sets the output current at each output equal

to a nominal 3.5 mA. A 100 Ω differential termination resistor

placed at the LVDS receiver inputs results in a nominal 350 mV

swing (or 700 mV p-p differential) at the receiver.

When operating in reduced range mode, the output current

reduces to 2 mA. This results in a 200 mV swing (or 400 mV p-p

differential) across a 100 Ω termination at the receiver.

The LVDS outputs facilitate interfacing with LVDS receivers in

custom ASICs and FPGAs for superior switching performance

in noisy environments. Single point-to-point net topologies are

recommended with a 100 Ω termination resistor placed as close

as possible to the receiver. Timing errors may result if there is

no far-end receiver termination, or if there is poor differential

trace routing. To avoid such timing errors, ensure that the trace

length is less than 24 inches and that the differential output

traces are close together and at equal lengths.

Figure 62 shows an example of the FCO and data stream with

proper trace length and position.

Figure 63 shows the LVDS output timing example in reduced

range mode.

D0 500mV/DIV

D1 500mV/DIV

DCO 500mV/DIV

FCO 500mV/DIV

4ns/DIV

Figure 62. LVDS Output Timing Example in ANSI-644 Mode (Default)

D0 400mV/DIV

D1 400mV/DIV

DCO 400mV/DIV

FCO 400mV/DIV

4ns/DIV

Figure 63. LVDS Output Timing Example in Reduced Range Mode

Rev. 0 | Page 24 of 37

AD9655 Datasheet(PDF) 25 Page - Analog Devices