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AD9259 Datasheet(PDF) 22 Page - Analog Devices |
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AD9259 Datasheet(HTML) 22 Page - Analog Devices |
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22 / 53 page  Data Sheet AD9259 Rev. E | Page 21 of 52 CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9259 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional biasing. Figure 42 shows a preferred method for clocking the AD9259. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. The back-to- back Schottky diodes across the secondary transformer limit clock excursions into the AD9259 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9259, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 0.1µF 0.1µF 0.1µF 0.1µF SCHOTTKY DIODES: HSM2812 CLK+ 50Ω 100Ω CLK– CLK+ ADC AD9259 Mini-Circuits® ADT1-1WT, 1:1Z XFMR Figure 42. Transformer-Coupled Differential Clock Another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 43. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515 of clock drivers offers excellent jitter performance. 100 Ω 0.1µF 0.1µF 0.1µF 0.1µF 240 Ω 240 Ω 50 Ω1 50 Ω1 CLK CLK 150 Ω RESISTORS ARE OPTIONAL. CLK– CLK+ ADC AD9259 AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 PECL DRIVER CLK+ CLK– Figure 43. Differential PECL Sample Clock 10 0Ω 0.1µF 0.1µF 0.1µF 0.1µF 50Ω* LVDS DRIVER 50Ω1 CLK CLK 1 50Ω RESISTORS ARE OPTIONAL CLK– CLK+ ADC AD9259 AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 CLK+ CLK– Figure 44. Differential LVDS Sample Clock In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be driven directly from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 45). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages of up to 3.3 V and therefore offers several selections for the drive logic voltage. 0.1µF 0.1µF 0.1µF 39k Ω CMOS DRIVER 50 Ω1 OPTIONAL 100 Ω 0.1µF CLK CLK 150 Ω RESISTOR IS OPTIONAL. CLK– CLK+ ADC AD9259 AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 CLK+ Figure 45. Single-Ended 1.8 V CMOS Sample Clock 0.1µF 0.1µF 0.1µF AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 CMOS DRIVER 50 Ω1 OPTIONAL 100Ω CLK CLK 150 Ω RESISTOR IS OPTIONAL. 0.1µF CLK– CLK+ ADC AD9259 CLK+ Figure 46. Single-Ended 3.3 V CMOS Sample Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9259 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9259. When the DCS is on, noise and distortion perfor- mance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the Memory Map section for more details on using this feature. Jitter in the rising edge of the input is an important concern, and it is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates of less than 20 MHz nominal. The loop has a time constant associated with it that must be considered in applications where the clock rate can change dynamically. This requires a wait time of 1.5 µs to 5 µs after a dynamic clock frequency increase (or decrease) before the DCS loop is relocked to the input signal. During the period that the loop is not locked, the DCS loop is bypassed and the internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. |
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