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AD9259 Datasheet(PDF) 25 Page - Analog Devices |
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AD9259 Datasheet(HTML) 25 Page - Analog Devices |
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25 / 53 page ![]() AD9259 Data Sheet Rev. E | Page 24 of 52 100 50 0 –100ps 0ps 100ps 500 –500 0 –1.0ns –0.5ns 0ns 0.5ns 1.0ns EYE: ALL BITS ULS: 10000/15600 0 Figure 50. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Less than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only 200 –200 0 –1.0ns –0.5ns 0ns 0.5ns 1.0ns EYE: ALL BITS ULS: 9600/15600 100 50 0 –150ps –100ps –50ps 0ps 50ps 100ps 150ps Figure 51. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Greater than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only 100 50 0 –150ps –100ps –50ps 0ps 50ps 100ps 150ps 200 400 –200 –400 0 –1.0ns –0.5ns 0ns 0.5ns 1.0ns EYE: ALL BITS ULS: 9599/15599 Figure 52. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Internal Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only The format of the output data is offset binary by default. An example of the output coding format can be found in Table 8. To change the output data format to twos complement, see the Memory Map section. Table 8. Digital Output Coding Code (VIN + x) − (VIN − x), Input Span = 2 V p-p (V) Digital Output Offset Binary (D13 ... D0) 16383 +1.00 11 1111 1111 1111 8192 0.00 10 0000 0000 0000 8191 −0.000122 01 1111 1111 1111 0 −1.00 00 0000 0000 0000 Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 14 bits times the sample clock rate, with a maximum of 700 Mbps (14 bits × 50 MSPS = 700 Mbps). The lowest typical conversion rate is 10 MSPS. However, if lower sample rates are required for a specific application, the PLL can be set up via the SPI to allow encode rates as low as 5 MSPS. See the Memory Map section for details on enabling this feature. |
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