AD9259 datasheet(31/53 Pages) AD

31 / 53 page

AD9259

Data Sheet

Rev. E | Page 30 of 52

NUMBER OF SDIO PINS CONNECTED TOGETHER

1.715

1.720

1.725

1.730

1.735

1.740

1.745

1.750

1.755

1.760

1.765

1.770

1.775

1.780

1.785

1.790

1.795

1.800

030

100

Figure 57. SDIO Pin Loading

If the user chooses not to use the SPI, these dual-function pins

serve their secondary functions when the CSB is strapped to

AVDD during device power-up. See the Theory of Operation

section for details on which pin-strappable functions are

supported on the SPI pins.

For users who wish to operate the ADC without using the

SPI, remove any connections from the CSB, SCLK/DTP, and

SDIO/ODM pins. By disconnecting these pins from the control

bus, the ADC can function in its most basic operation. Each

of these pins has an internal termination that floats to its

respective level.

DON’T CARE

SDIO

SCLK

CSB

tDH

tHI

tCLK

tLO

tDS

R/W

A12

A11

A10

Figure 58. Serial Timing Details

Table 15. Serial Timing Definitions

Parameter

Timing (Minimum, ns)

Description

tDS

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the clock

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHI

Minimum period that SCLK should be in a logic high state

tLO

Minimum period that SCLK should be in a logic low state

tEN_SDIO

Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK

falling edge (not shown in Figure 58)

tDIS_SDIO

Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK

rising edge (not shown in Figure 58)

AD9259 Datasheet(PDF) 31 Page - Analog Devices

AD9259 Datasheet(HTML) 31 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Datasheet Download

Link URL