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TUSB1044 Datasheet(PDF) 3 Page - Texas Instruments |
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TUSB1044 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 67 page ![]() 6 5 4 3 2 1 13 14 15 16 17 18 19 20 21 22 23 24 12 11 10 9 8 7 25 28 26 27 36 35 34 33 32 31 30 29 37 38 39 40 DTX2p DRX1p UTX2p URX2p DRX2p UTX1n UTX1p DTX2n UTX2n URX2n DRX1n DRX2n URX1n URX1p HPDIN DTX1p DTX1n UEQ0/A0 DEQ1 I2C_EN VIO_SEL DEQ0 VCC Thermal Pad GND DIR1 3 TUSB1044 www.ti.com SLLSF47A – FEBRUARY 2018 – REVISED FEBRUARY 2018 Product Folder Links: TUSB1044 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated 5 Pin Configuration and Functions RNQ Package 40-Pin (WQFN) Top View Pin Functions PIN I/O DESCRIPTION NO. NAME 1 VCC P 3.3 V Power Supply 2 UEQ1/A1 4 Level I This pin along with UEQ0 sets the high-frequency equalizer gain for upstream facing URX1, URX2, UTX1, UTX2 receivers. In I2C Mode, this pin will also set TUSB1044 I2C address. Refer to Table 9. 3 CFG0 4 Level I CFG0. This pin along with CFG1 will select VOD linearity range and DC gain for all the downstream and upstream channels. Refer to Table 8 for VOD linearity range and DC gain options. 4 CFG1 4 Level I CFG1. This pin along with CFG0 will set VOD linearity range and DC gain for all the downstream and upstream channels. Refer to Table 8 for VOD linearity range and DC gain options. 5 SWAP 2 Level I This pin swaps all the channel directions and EQ settings of downstream facing and upstream facing data path inputs. 0 – Do not swap channel directions and EQ settings (Default) 1. – Swap channel directions and EQ settings. 6 VCC P 3.3V Power Supply 7 SLP_S0# 2 Level I This pin when asserted low will disable Receiver Detect functionality. While this pin is low and TUSB1044 is in U2/U3, TUSB1044 will disable LOS and LFPS detection circuitry and RX termination for both channels will remain enabled. If this pin is low and TTUSB1044 is in Disconnect state, the RX detect functionality will be disabled and RX termination for both channels will be disabled. 0 – RX Detect disabled 1 – RX Detect enabled (Default) 8 DIR0 2 Level I This pin along with DIR1 sets the data path signal direction format. Refer to Table 4 for signal direction formats. 0 - Source Side (DFP) Alt Mode format 1 - Sink Side (UFP) Alt Mode format 9 URX2p Diff I/O Differential positive input/output for upstream facing RX2 port. 10 URX2n Diff I/O Differential negative input/output for upstream facing RX2 port. |
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