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TUSB1044 Datasheet(PDF) 11 Page - Texas Instruments |
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TUSB1044 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 67 page  tBUF tHDSTA tR tLOW tHDDAT tHIGH tF tSUDAT tSUSTA tHDSTA tSUSTO P S S P SDA SCL 30% 70% 30% 70% 11 TUSB1044 www.ti.com SLLSF47A – FEBRUARY 2018 – REVISED FEBRUARY 2018 Product Folder Links: TUSB1044 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated 6.7 Timing Requirements MIN NOM MAX UNIT I2C Timing fSCL I2C clock frequency 1 MHz tBUF Bus free time between START and STOP conditions 0.5 µs tHDSTA Hold time after repeated START condition. After this period, the first clock pulse is generated 0.26 µs tLOW Low period of the I2C clock 0.5 µs tHIGH High period of the I2C clock 0.26 µs tSUSTA Setup time for a repeated START condition 0.26 µs tHDDAT Data hold time 0 µs tSUDAT Data setup time 50 ns tR Rise time of both SDA and SCL signals 120 ns tF Fall time of both SDA and SCL signals 20 × (VI2C/5.5 V) 120 ns tSUSTO Setup time for STOP condition 0.26 µs CBUS Capacitive load for each bus line 100 pF HPDIN and CTL1 tCTL1_DEBO UNCE CTL1 and HPDIN debounce time when transitioning from H to L. DP lanes will be disabled if low is greater than min value. 2.5 ms USB3.1 and DisplayPort mode transition requirement GPIO mode tGP_USB_4D P Min overlap of CTL0 and CTL1 when transitioning from USB 3.1 only mode to 4-Lane DisplayPort mode or vice versa. Refer to Figure 2 4 µs Power-on timings td_pg VCC(MIN) to Internal power good asserted high. Refer to Figure 8 500 µs tcfg_su CFG pins setup. Refer to Figure 8 350 µs tcfg_hd CFG pin hold. Refer to Figure 8 10 µs tctl_db CTL[1:0] and FLIP pin debounce. Refer to Figure 8 16 ms tVCC_RAMP VCC supply ramp requirement. Refer to Figure 8 0.1 100 ms Figure 1. I2C Timing Diagram Definitions |
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