TUSB1044 datasheet(4/67 Pages) TI1

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TUSB1044

SLLSF47A – FEBRUARY 2018 – REVISED FEBRUARY 2018

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Pin Functions (continued)

I/O

DESCRIPTION

NO.

NAME

DIR1

2 Level I/O

This pin along with DIR0 sets the data path signal direction format. Refer to Table 4 for signal direction

formats.

0 - DisplayPort Alt Mode format

1 - Custom Alt Mode format

UTX2p

Diff I/O

Differential positive input/output for upstream facing TX2 port.

UTX2n

Diff I/O

Differential negative input/output for upstream facing TX2 port.

VIO_SEL

4 Level I/O

This pin selects I/O voltage levels for the 2-level GPIO configuration pins and the I2C interface:

0 = 3.3-V configuration I/O voltage, 3.3-V I2C interface (Default)

R = 3.3-V configuration I/O voltage, 1.8-V I2C interface

F = 1.8-V configuration I/O voltage, 3.3-V I2C interface

1 = 1.8-V configuration I/O voltage, 1.8-V I2C interface.

UTX1n

Diff I/O

Differential negative input/output for upstream facing TX1 port.

UTX1p

Diff I/O

Differential positive input/output for upstream facing TX1 port.

I2C_EN

4 Level I

I2C Programming or Pin Strap Programming Select.

0 = GPIO Mode, AUX Snoop Enabled (I2C disabled)

R = TI Test Mode (I2C enabled)

F = GPIO Mode, AUX Snoop Disabled (I2C disabled)

1 = I2C enabled.

URX1n

Diff I/O

Differential negative input/output for upstream facing RX1 port.

URX1p

Diff I/O

Differential positive input/output for upstream facing RX1 port.

VCC

3.3V Power Supply

FLIP/SCL

2 Level I

(Failsafe)

In GPIO mode, this is Flip control pin, otherwise this pin is I2C clock.

CTL0/SDA

2 Level I

(Failsafe)

In GPIO mode, this is a USB3.1 Switch control pin, otherwise this pin is I2C data.

CTL1

2 Level I

(PD)

DP Alt mode Switch Control Pin. In GPIO mode, this pin will enable or disable DisplayPort functionality.

Otherwise DisplayPort functionality is enabled and disabled through I2C registers.

L = DisplayPort Disabled.

H = DisplayPort Enabled.

In I2C Mode, this pin is not used by TUSB1044.

AUXp

I/O,

CMOS

AUXp. DisplayPort AUX positive I/O connected to the DisplayPort source or sink through an AC coupling

capacitor. In addition to AC coupling capacitor, this pin also requires a 100-kΩ resistor to GND between

the AC coupling capacitor and the AUXp pin if the TUSB1044 is used on the DisplayPort source side, or a

1-MΩ resistor to DP_PWR (3.3V) between the AC coupling capacitor and the AUXp pin if TUSB1044 is

used on the DisplayPort sink side. This pin along with AUXn is used by the TUSB1044 for AUX snooping

and is routed to SBU1/2 based on the orientation of the Type-C plug.

AUXn

I/O,

CMOS

AUXn. DisplayPort AUX I/O connected to the DisplayPort source or sink through an AC coupling

capacitor. In addition to AC coupling capacitor, this pin also requires a 100-kΩ resistor to DP_PWR (3.3V)

between the AC coupling capacitor and the AUXn pin if the TUSB1044 is used on the DisplayPort source

side, or a 1-MΩ resistor to GND between the AC coupling capacitor and the AUXn pin if TUSB1044 is

used on the DisplayPort sink side. This pin along with AUXp is used by the TUSB1044 for AUX snooping

and is routed to SBU1/2 based on the orientation of the Type-C plug.

SBU2

I/O,

CMOS

SBU2. When the TUSB1044 is used on the DisplayPort source side, this pin should be DC coupled to the

SBU2 pin of the Type-C receptacle. When the TUSB1044 is used on the DisplayPort sink side, this pin

should be DC coupled to the SBU1 pin of the Type-C receptacle. A 2-MΩ resistor to GND is also

recommended.

SBU1

I/O,

CMOS

SBU1. When the TTUSB1044 is used on the DisplayPort source side, this pin should be DC coupled to

the SBU1 pin of the Type-C receptacle. When the TUSB1044 is used on the DisplayPort sink side, this pin

should be DC coupled to the SBU2 pin of the Type-C receptacle. A 2-MΩ resistor to GND is also

recommended.

VCC

3.3V Power Supply

DEQ1

4 Level I

This pin along with DEQ0 sets the high-frequency equalizer gain for downstream facing DRX1, DRX2,

DTX1, DTX2 receivers.

DRX1p

Diff I/O

Differential positive input/output for downstream facing RX1 port.

DRX1n

Diff I/O

Differential negative input/output for downstream facing RX1 port.

HPDIN

2 Level I (PD)

This pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is low for greater

than 2ms, all DisplayPort lanes are disabled and AUX to SBU switch will remain closed. When HPDIN is

high, the enabled DisplayPort lanes from AUX snoop or registers will be active.

DTX1p

Diff I/O

Differential positive input/output for downstream facing TX1 port.

DTX1n

Diff I/O

Differential negative input/output for downstream facing TX1 port.

UEQ0/A0

4 Level I

This pin along with UEQ1 sets the high-frequency equalizer gain for upstream facing URX1, URX2, UTX1,

UTX2 receivers. In I2C mode, this pin will also set TUSB1044 I2C address. Refer to Table 9.

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