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S71PL254 Datasheet(PDF) 161 Page - SPANSION |
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S71PL254 Datasheet(HTML) 161 Page - SPANSION |
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161 / 196 page ![]() June 15, 2004 SRAM_Type01_02A0 SRAM 161 Advance I n f o rmatio n Notes: 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. Figure 81. Timing Waveform of Read Cycle(2) (WE#=VIH, if BYTE# is Low, Ignore UB#/LB# Timing) Figure 82. Timing Waveform of Write Cycle(1) (WE# controlled, if BYTE# is Low, Ignore UB#/LB# Timing) High-Z tRC tOH tAA tCO1 tBA tOE tOLZ tBLZ tLZ tOHZ tBHZ tHZ tCO2 Address CS1# CS2 UB#, LB# OE# Data out Data Valid tWC tCW(2) tWR(4) tAW tBW tWP(1) tAS(3) tDH tDW tWHZ tOW High-Z High-Z tCW(2) Address CS1# CS2 UB#, LB# WE# Data in Data out Data Undefined Data Valid |
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