S71PL254 datasheet(162/196 Pages) SPANSION

162 / 196 page

162

SRAM

SRAM_Type01_02A0 June 15, 2004

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I n f o rmation

Figure 83. Timing Waveform of Write Cycle(2) (CS# controlled, if BYTE# is Low, Ignore UB#/LB# Timing)

Notes:

1. A write occurs during the overlap (tWP) of low CS1# and low WE#. A write begins when CS1# goes low and WE#

goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double

byte operation. A write ends at the earliest transition when CS1# goes high and WE# goes high. The tWP is

measured from the beginning of write to the end of write.

2. tCW is measured from the CS1# going low to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1# or WE#

going high.

Figure 84. Timing Waveform of Write Cycle(3) (UB#, LB# controlled)

High-Z

tWC

tCW(2)

tAW

tBW

tWP(1)

tDH

tDW

tWR(4)

tAS(3)

Address

CS1#

CS2

UB#, LB#

WE#

Data in

Data out

Data Valid

High-Z

tWC

tCW(2)

tBW

tWP(1)

tDH

tDW

tWR(4)

tAW

tAS(3)

tCW(2)

Address

CS1#

CS2

UB#, LB#

WE#

Data in

Data out

Data Valid

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