S71PL254 datasheet(189/196 Pages) SPANSION

189 / 196 page

June 8, 2004 pSRAM_Type01_12_A0

pSRAM Type 1

189

Advance

I n f o rmatio n

transitioning high and the mode remains active until the register is updated. To

return to the full 32Mb address space, the VA register must be reset using the

previously defined procedures. While operating in the RMS mode, the unselected

portion of the array may not be used.

Other Mode Register Settings (for 64M)

The Page Mode operation can also be enabled and disabled using the Mode Reg-

ister. Register bit A7 controls the operation of Page Mode and setting this bit to a

one (1), enables Page Mode. If the register bit A7 is set to a zero (0), Page Mode

operation is disabled.

Figure 93. Mode Register

Deep Sleep Enable/Disable

0 = Deep Sleep Enabled

1 = Deep Sleep Disabled (default)

PAR Section

1 = Top 1/4 array

0 = Top 1/2 array

1 = Top 3/4 array

0 = No PAR

1 = Bottom 1/4 array

0 = Bottom 1/2 array

1 = Bottom 3/4 array

0 = Full array (default)

Reserved

Must set to all 0

A21 - A8

Page Mode

0 = Page Mode Disabled (default)

1 = Page Mode Enabled

Temp

Compensated

Refresh

0 = 15oC

1 = 45oC

0 = 70oC

1 = 85oC (default)

Array Mode

for ZZ#

0 = PAR (default)

1 = RMS

64 Mb

32 Mb / 16 Mb

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