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S71PL254 Datasheet(PDF) 191 Page - SPANSION |
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S71PL254 Datasheet(HTML) 191 Page - SPANSION |
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191 / 196 page  June 8, 2004 pSRAM_Type01_12_A0 pSRAM Type 1 191 Advance I n f o rmatio n Mode Register Update and Deep Sleep Timings Notes: 1. Minimum cycle time for writing register is equal to speed grade of product. Address Patterns for PASR (A4=1) (64M) Item Symbol Min Max Unit Note Chip deselect to ZZ# low tCDZZ 5 ns ZZ# low to WE# low tZZWE 10 500 ns Write register cycle time tWC 70/85 ns 1 Chip enable to end of write tCW 70/85 ns 1 Address valid to end of write tAW 70/85 ns 1 Write recovery time tWR 0 ns Address setup time tAS 0 ns Write pulse width tWR 40 ns Deep Sleep Pulse Width tZZMIN 10 µs Deep Sleep Recovery tR 150 µs A2 A1 A0 Active Section Address Space Size Density 1 1 1 Top quarter of die 300000h-3FFFFFh 1Mb x 16 16Mb 1 1 0 Top half of die 200000h-3FFFFFh 2Mb x 16 32Mb 1 0 1 Reserved 1 0 0 No PASR None 0 0 0 1 1 Bottom quarter of die 000000h-0FFFFFh 1Mb x 16 16Mb 0 1 0 Bottom half of die 000000h-1FFFFFh 2Mb x 16 32Mb 0 0 1 Reserved 0 0 0 Full array 000000h-3FFFFFh 4Mb x 16 64Mb |
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