AM3351 datasheet(175/252 Pages) TI1

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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351

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SPRS717J – OCTOBER 2011 – REVISED APRIL 2016

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Peripheral Information and Timings

Table 7-60. PCB Stackup Specifications(1)

NO.

PARAMETER

MIN

TYP

MAX

UNIT

PCB routing and plane layers

Signal routing layers

Full ground reference layers under DDR3 routing region(2)

Full VDDS_DDR power reference layers under the DDR3 routing region(2)

Number of reference plane cuts allowed within DDR3 routing region(3)

Number of layers between DDR3 routing layer and reference plane(4)

PCB routing feature size

mils

PCB trace width, w

mils

PCB BGA escape via pad size(5)

mils

PCB BGA escape via hole size

mils

Single-ended impedance, Zo(6)

Impedance control(7)(8)

Zo-5

Zo+5

(1) For the DDR3 device BGA pad size, see the DDR3 device manufacturer documentation.

(2) Ground reference layers are preferred over power reference layers. Be sure to include bypass capacitors to accommodate reference

layer return current as the trace routes switch routing layers.

(3) No traces should cross reference plane cuts within the DDR3 routing region. High-speed signal traces crossing reference plane cuts

create large return current paths which can lead to excessive crosstalk and EMI radiation.

(4) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.

(5) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available

for power routing. An 18-mil pad is required for minimum layer count escape.

(6) Zo is the nominal singled-ended impedance selected for the PCB.

(7) This parameter specifies the AC characteristic impedance tolerance for each segment of a PCB signal trace relative to the chosen Zo

defined by the single-ended impedance parameter.

(8) Tighter impedance control is required to ensure flight time skew is minimal.

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