AM3351 datasheet(174/252 Pages) TI1

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174

AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351

SPRS717J – OCTOBER 2011 – REVISED APRIL 2016

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Peripheral Information and Timings

7.7.2.3.3.2 Compatible JEDEC DDR3 Devices

Table 7-58 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.

Table 7-58. Compatible JEDEC DDR3 Devices (Per Interface)

NO.

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

JEDEC DDR3 device speed grade

tC(DDR_CK) and tC(DDR_CKn)

= 3.3 ns

DDR3-800

tC(DDR_CK) and tC(DDR_CKn)

= 2.5 ns

DDR3-1600

JEDEC DDR3 device bit width

x16

bits

JEDEC DDR3 device count(1)

devices

(1) For valid DDR3 device configurations and device counts, see Section 7.7.2.3.3.1, Figure 7-47, and Figure 7-49.

7.7.2.3.3.3 PCB Stackup

The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 7-59.

Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal

integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.

Table 7-59. Minimum PCB Stackup(1)

LAYER

TYPE

DESCRIPTION

Signal

Top signal routing

Plane

Ground

Plane

Split Power Plane

Signal

Bottom signal routing

(1) All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these

signals on layer 1, therefore requiring routing of some signals on layer 4. When this is done, the signal routes on layer 4 must not cross

splits in the power plane.

AM3351 Datasheet(PDF) 174 Page - Texas Instruments

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