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AM3351 Datasheet(PDF) 224 Page - Texas Instruments

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Part # AM3351
Description  Sitara Processors
PDF  252 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM3351 Datasheet(HTML) 224 Page - Texas Instruments

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CLOCKOUT
DATAOUT
1
3
4
2
6
5
DATAIN
1
3
4
2
224
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
SPRS717J – OCTOBER 2011 – REVISED APRIL 2016
www.ti.com
Submit Documentation Feedback
Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351
Peripheral Information and Timings
Copyright © 2011–2016, Texas Instruments Incorporated
(1)
P = L3_CLK (PRU-ICSS ocp clock) period.
Figure 7-100. PRU-ICSS PRU Shift In Timing
Table 7-96. PRU-ICSS PRU Switching Requirements - Shift Out Mode
(see Figure 7-101)
NO.
MIN
MAX
UNIT
1
tc(CLOCKOUT)
Cycle time, CLOCKOUT
10.00
ns
2
tw(CLOCKOUT)
Pulse width, CLOCKOUT
0.45 × P(1)
0.55 × P(1)
ns
3
tr(CLOCKOUT)
Rising time, CLOCKOUT
1.00
3.00
ns
4
tf(CLOCKOUT)
Falling time, CLOCKOUT
1.00
3.00
ns
5
td(CLOCKOUT-DATAOUT)
Delay time, CLOCKOUT to DATAOUT valid
0.00
3.00
ns
6
tr(DATAOUT)
Rising time, DATAOUT
1.00
3.00
ns
tf(DATAOUT)
Falling time, DATAOUT
1.00
3.00
ns
Figure 7-101. PRU-ICSS PRU Shift Out Timing
7.14.2
PRU-ICSS EtherCAT (PRU-ICSS ECAT)
Table 7-97. PRU-ICSS ECAT Timing Conditions
PARAMETER
MIN
MAX
UNIT
Output Condition
Cload
Capacitive load for each bus line
30
pF
7.14.2.1 PRU-ICSS ECAT Electrical Data and Timing
Table 7-98. PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
(see Figure 7-102)
NO.
MIN
MAX
UNIT
1
tw(EDIO_LATCH_IN)
Pulse width, EDIO_LATCH_IN
100.00
ns
2
tr(EDIO_LATCH_IN)
Rising time, EDIO_LATCH_IN
1.00
3.00
ns
3
tf(EDIO_LATCH_IN)
Falling time, EDIO_LATCH_IN
1.00
3.00
ns
4
tsu(EDIO_DATA_IN-
EDIO_LATCH_IN)
Setup time, EDIO_DATA_IN valid before EDIO_LATCH_IN
active edge
20.00
ns
5
th(EDIO_LATCH_IN-
EDIO_DATA_IN)
Hold time, EDIO_DATA_IN valid after EDIO_LATCH_IN active
edge
20.00
ns



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