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AM3351 Datasheet(PDF) 229 Page - Texas Instruments |
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AM3351 Datasheet(HTML) 229 Page - Texas Instruments |
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229 / 252 page  MII_MRCLK (Input) 1 2 MII_RXD[3:0], MII_RXDV, MII_RXER (Inputs) MII_TXCLK 2 3 1 4 4 229 AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351 www.ti.com SPRS717J – OCTOBER 2011 – REVISED APRIL 2016 Submit Documentation Feedback Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright © 2011–2016, Texas Instruments Incorporated Table 7-108. PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK (see Figure 7-110) NO. 10 Mbps 100 Mbps UNIT MIN TYP MAX MIN TYP MAX 1 tc(TX_CLK) Cycle time, TX_CLK 399.96 400.04 39.996 40.004 ns 2 tw(TX_CLKH) Pulse duration, TX_CLK high 140 260 14 26 ns 3 tw(TX_CLKL) Pulse duration, TX_CLK low 140 260 14 26 ns 4 tt(TX_CLK) Transition time, TX_CLK 3 3 ns Figure 7-110. PRU-ICSS MII_TXCLK Timing Table 7-109. PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER (see Figure 7-111) NO. 10 Mbps 100 Mbps UNIT MIN TYP MAX MIN TYP MAX 1 tsu(RXD-RX_CLK) Setup time, RXD[3:0] valid before RX_CLK 8 8 ns tsu(RX_DV-RX_CLK) Setup time, RX_DV valid before RX_CLK tsu(RX_ER-RX_CLK) Setup time, RX_ER valid before RX_CLK 2 th(RX_CLK-RXD) Hold time RXD[3:0] valid after RX_CLK 8 8 ns th(RX_CLK-RX_DV) Hold time RX_DV valid after RX_CLK th(RX_CLK-RX_ER) Hold time RX_ER valid after RX_CLK Figure 7-111. PRU-ICSS MII_RXD[3:0], MII_RXDV, and MII_RXER Timing |
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