80C86

FN2957 Rev 4.00

Page 20 of 38

August 19, 2015

Waveforms

FIGURE 7A. BUS TIMING - MINIMUM MODE SYSTEM

NOTE: Signals at 82C84A are shown for reference only. RDY is sampled near the end of t2, t3, tW to determine if TW machine states are to be

inserted.

TCVCTX

(31)

(29) TCVCTV

DEN

DT/R

(30)

TCHCTV

TCLRL

(33)

(30)

TCHCTV

READ CYCLE

(35)

(34) TCLRH

RD

DATA IN

(7)

TCLDX1

(10)

TRYHCH

AD15-AD0

(24)

(17)

TCLAV

READY (80C86 INPUT)

RDY (82C84A INPUT)

SEE NOTE

ALE

BHE/S7, A19/S6-A16/S3

(17)

TCLAV

M/IO

(30) TCHCTV

CLK (82C84A OUTPUT)

(3)

TCHCL

TCH1CH2

(4)

(2)

TCLCH

TCHCTV

(30)

(5)

TCL2CL1

t1

t2

t3

t4

(1)

TCLCL

(26) TCLDV

(18) TCLAX

BHE, A19-A16

(23) TCLLH

TLHLL

(22)

TLLAX

(25)

TCHLL

TAVAL

(39)

(12)

TRYLCL

(11)

TCHRYX

(19)

TCLAZ

(16)

TDVCL

AD15-AD0

TRHAV

(32) TAZRL

TRLRH

(37)

TCLR1X (9)

TR1VCL (8)

S7-S3