TVP3025 datasheet(39/99 Pages) TI

39 / 99 page

2–25

Table 2–9. Pseudo-Color Mode Pixel-Latching Sequence (see Note 15)

VGA7–VGA0

P1, P0

P1 – P0

P3, P2

P3 – P2

P5 – P4

•

P7 – P6

•

P15

P31

P63

s10

s11

s12

s13

s14

s15

P1 – P0

P3 – P0

P3 – P2

P7 – P4

P5 – P4

P11–P8

•

P15 – P12

•

P15 – P14

P31 – P30

P63 – P62

P31 – P28

P63 – P60

s16

s17

s18

s19

P7 – P0

P15 – P8

P23 – P16

P31 – P24

•

P63 – P56

NOTE 15: The latching sequence is initiated by a rising edge on LCLK. For modes in which multiple groups of data are

latched, the LCLK rising edge latches all the groups and the pixel clock shifts them out starting with the

low-numbered group. For example, in pseudo-color submode 3 with a 16-bit pixel bus width, the rising edge

of LCLK latches all the data groups shown above (s13) and the pixel clock shifts them out in the order P(3 – 0),

P(7 – 4), P(11 – 8), and P(15 – 12). Note that each line in each subtable above represents one pixel.

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