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TVP3025 Datasheet(PDF) 71 Page - Texas Instruments

Part # TVP3025
Description  Video Interface Palette
PDF  99 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TVP3025 Datasheet(HTML) 71 Page - Texas Instruments

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2–57
2.4.15.2 Command Register 1 (RS value = 11000)
Writing to command register 1 (or at device reset) sets output-clock-selection register bits 2, 5, and 6 to
logic 0.
Table 2–24. Command Register 1 (RS value = 11000)
BIT
NAME
VALUES
DESCRIPTION
CR17
Reserved
CR17
Reserved
00: 24 bits/pixel
CR16,
01: 16 bits/pixel
Operation mode selection See Section 2 4 10 and Tables 2 18 through 2 21
,
15
10: 8 bits/pixel
Operation mode selection. See Section 2.4.10 and Tables 2–18 through 2–21.
11: 4 bits/pixel
CR14
0: Nonbypass (default)
This bit must be set to logic 1 for BT485 mode true color operation using the
CR14
1: Palette bypass
gg
TVP3025.
CR13
0: 5:5:5 RGB format
(default)
16 bit/pixel data format select. See Section 2.4.10.3 and Tables 2–18 through
2–20
1: 5:6:5 RGB format
2–20.
CR12
0:
16 bit/pixel multiplex mode select. Not supported on the TVP3025. The default
CR12
1:
is 2:1, but 4:1 can be selected with CR40.
CR11
0:
16 bit real time switch Not supported on the TVP3025
CR11
1:
16 bit real time switch. Not supported on the TVP3025.
CR10
0:
16 bit/pixel port switch control Not supported on the TVP3025
CR10
1:
16 bit/pixel port switch control. Not supported on the TVP3025.
NOTE: The following command register 1 bits are written into the following TVP3025 indirect register bits: CR13 into
multiplexer-control register 1 bit 0, CR14 into multiplexer-control register 1 bit 6, CR15 into multiplexer-control
register 2 bit 3, CR15 into output-clock-selection register bits 0 and 3, CR15 into multiplexer-control register 1
bit 1, CR15 into multiplexer-control register 1 bit 3, CR16 into multiplexer-control register 1 bit 7, and CR16 into
output-clock-selection register bits 1 and 4.
These registers are not initialized at power up. All command registers are set to a logic 0 when a low signal is
asserted at the RESET terminal.



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