TVP3025 datasheet(11/99 Pages) TI

11 / 99 page

1–5

1.4

Ordering Information

TVP3025

– XXX

XXX

Pixel Clock Frequency Indicator

MUST CONTAIN THREE CHARACTERS:

– 135: 135-MHz pixel clock

– 175: 175-MHz pixel clock

– 220: 220-MHz pixel clock

Package

MUST CONTAIN THREE LETTERS:

MDN: Metal, Quad Flat Pack

PCE:

Plastic, Quad Flat Pack (mechanical data unavailable at time of print)

1.5

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AVDD

84, 86

Analog power. All AVDD terminals must be connected.

CLK0

106

(TTL

compatible)

Dot clock 0 input. CLK0 can be selected to drive the dot clock at

frequencies up to 140 MHz. When VGA mode is active, the selected

clock source is CLK0. The maximum frequency in VGA mode is 85 MHz.

The maximum frequency for direct color/VGA switching in self-clocked

mode is 50MHz. This clock source is also selected at reset.

CLK1

107

(TTL

compatible)

Dot clock 1 input. CLK1 can be selected to drive the dot clock at

frequencies up to 140 MHz.

CLK2,

CLK2

108, 109

(TTL/ECL

compatible)

Dual-mode dot clock input. These inputs are essentially ECL-

compatible inputs, but two TTL clocks may be used on CLK2 and CLK2

if so selected in the input-clock-selection register. These inputs may be

selected as the dot clock up to the device limit while in the ECL mode

or up to 140 MHz in the TTL mode.

COMP1,

COMP2

77, 79

Compensation. COMP1 and COMP2 provide compensation for the

internal reference amplifier. A 0.1-

µF ceramic capacitor is required

between COMP1 and COMP2. This capacitor must be as close to the

device as possible for proper decoupling and to avoid noise pick up.

DCLK

122

Dot clock. Divided memory clock output. A frequency divided version of

the MCLK output.

DVDD

18, 45, 65,

117, 137, 143,

148

Digital power. All DVDD terminals must be connected.

D0 – D7

47 – 54

I/O

(TTL

compatible)

MPU interface data bus. These terminals are used to transfer data in and

out of the register map and palette/overlay RAM.

FS ADJUST

Full-scale adjustment. A resistor connected between this terminal and

ground controls the full-scale range of the DACs.

GND

17, 46, 66, 69,

71, 73, 75, 83,

85, 118, 136,

142, 147

Ground. All GND terminals must be connected. The GNDs are

connected internally.

NOTE: All unused inputs should be tied to a logic level and not be allowed to float.

TVP3025 Datasheet(PDF) 11 Page - Texas Instruments

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