TVP3025 datasheet(17/99 Pages) TI

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2–3

2.1.2

TVP3025/BT485 Register Initialization

The MODE1 input determines how the TVP3025 initializes at reset (using the RESET terminal). Upon device

reset, if MODE1 is logic 1, the TVP3025 initializes using the BT485 emulation register map (see Table 2–2)

and assumes BT485 compatible functionality. All internal BT485 type command registers and data registers

are reset to 00 (hex). On the rising edge of the RESET signal, the BT485 emulator translates all of the BT485

internal registers into the TVP3025 indirect registers. It also causes the internal emulator state machine to

begin monitoring BT485 register accesses and the cursor RAM interface is set to the planar access mode

(TVP3025 cursor control register bit 7 = 1). The translated TVP3025 indirect register map reset defaults for

the BT485 mode are shown in Table 2–3.

Additionally, the MCLK and pixel clock PLLs are enabled and set to approximately 45 MHz and 25 MHz,

respectively (with an external 14.318 MHz crystal). Also, all command registers are reset to zeroes and

blank/sync are configured to be latched on the rising edge of LCLK.

If MODE1 is logic 0 when the TVP3025 is reset, the device initializes the TVP3025 register maps as specified

in Table 2–1 and Table 2–3 and translation of the BT485 emulation registers does not take place. Also, the

cursor RAM interface is set to the nonplanar access mode (TVP3025 cursor control register bit 7 = 0) with

the same operation as the TVP3020. The internal BT485 registers can subsequently be programmed via

the RS4 or the MODE2 terminals.

The MODE2 terminal optionally inverts the RS4 register select signal internal to the device. This allows the

TVP3025 to be used with graphics controllers that support either four or five register selects. For designs

using only four register selects (RS0–RS3), RS4 should be connected to DVDD or GND and the MODE2

terminal can be used to select between the TVP3025 register map and the BT485 emulation register map

(see Tables 2–1 and 2–2). When the MODE2 input terminal is logic 0, the RS4 signal is internally inverted.

If MODE2 is logic 1, no inversion takes place. MODE2 is internally pulled up so that no inversion occurs if

the terminal is not connected. For designs using all five register selects (RS0 – RS4), both of the register

maps are available with RS4 performing the switching.

Note that general I/O terminal I/O4 is provided through the BT485 command register 4 and can be used to

externally connect to RS4.

Table 2–3. TVP3025 Indirect Register Map (Extended Registers)

INDEX REGISTER

(HEX)

R/W

DEFAULT

TVP3025

DEFAULT

BT485

BY INDEX REGISTER

0000

R/W

Cursor-Position X LSB

0001

R/W

Cursor-Position X MSB

0002

R/W

Cursor-Position Y LSB

0003

R/W

Cursor-Position Y MSB

0004

R/W

Sprite-Origin X

0005

R/W

Sprite-Origin Y

0006

R/W

Cursor-Control

0007

Reserved

0008

Cursor-RAM Address LSB

0009

Cursor-RAM Address MSB

000A

R/W

Cursor-RAM Data

000B

Reserved

000C – 000D

Reserved-Undefined

NOTE: Reserved registers should be avoided; otherwise, circuit behavior could deviate from

that specified. Reserved-undefined registers are nonexistent locations on the register

map.

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