TVP3025 datasheet(24/99 Pages) TI

24 / 99 page

2–10

Table 2–6. MCLK/DCLK Control Register (Index 0039 hex)

BIT NAME

VALUES

DESCRIPTION

MDCR7

0: Disable (default)

1: Enable

DCLK output enable bit.

MDCR6,

MDCR5, MDCR4

000: Divide by 2 (default)

001: Divide by 4

010: Divide by 6

011: Divide by 8

100: Divide by 10

101: Divide by 12

110: Divide by 14

111: Divide by 16

DCLK divide ratio. These bits specify the factor by which the MCLK

PLL is divided by before being output on the DCLK output terminal.

MDCR3

0: Disable

1: Enable (default)

MCLK output enable bit.

MDCR2,

MDCR1, MDCR0

000: Divide by 2 (default)

001: Divide by 4

010: Divide by 6

011: Divide by 8

100: Divide by 10

101: Divide by 12

110: Divide by 14

111: Divide by 16

MCLK divide ratio. These bits specify the factor by which the MCLK

PLL is divided by before being output on the MCLK output terminal.

Divide ratios are identical to those specified by bits MDCR6 – MDCR4

for the DCLK divider.

If P value register bit 7 is set to logic 0, then the PLL is disabled upon writing to the corresponding N value

bit 7 is set to logic 1, then the PLL is always enabled. If the pixel clock PLL is to be used for pixel clock

generation after it has been programmed, the input clock selection register must be set to 05 (hex).

At device reset, the loop clock PLL is disabled and reset, while the MCLK PLL and pixel clock PLL are

programmed to give approximately 45 MHz and 25 MHz outputs, respectively with a standard 14.318 MHz

crystal reference. For MCLK M = 9, N = 5, P = 1, MCLK/DCLK control = 08 (hex). For pixel clock M = 5,

N = 6, P=2.

All PLLs should be programmed such that FREF/(N + 2) u1 MHz and 110 MHz v(FVCO)v220 MHz for

proper operation. Also, N and M should be minimized, but

w1.

For pixel clock PLL output on the PCLKOUT terminal, the pixel clock P value register bit 3 must be set to

logic 1.

For the pixel clock PLL to be used as the pixel clock source, it must be selected in the input clock selection

If the MCLK PLL is used to clock the graphics controller, in general, the P value register bit 7 should be set

to logic 1 the first time the PLL is written so that the PLL always remains enabled. Otherwise, system lock-up

could occur.

TVP3025 Datasheet(PDF) 24 Page - Texas Instruments

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