TVP3025 datasheet(72/99 Pages) TI

72 / 99 page

2–58

2.4.15.3 Command Register 2 (RS value = 11001)

Writing to command register 2 sets input-clock-selection register (see Table 2–5) bits 1 and 2 to logic 0. Also,

cursor-control register (see Section 2.3.18.3) bits 2 and 5 are set to logic 0.

Table 2–25. Command Register 2 (RS value = 11001)

BIT

NAME

VALUES

DESCRIPTION

CR27

SCLK disable Not supported in the BT485 mode of the TVP3025

CR27

SCLK disable. Not supported in the BT485 mode of the TVP3025.

CR26

Reserved (logic 0)

CR26

Reserved (logic 0)

CR25

0: VGA mode (default)

VGA mode select. Unlike the BT485, this bit solely controls the switching

CR25

1: NonVGA mode

between modes. PSEL is disregarded.

CR24

0: CLK0 selected (default)

Pixel clock input select

CR24

1: CLK1 selected

Pixel clock input select

CR23

Noninterlaced / interlaced display selection. Interlaced mode is not supported

CR23

on the TVP3025. This bit is don’t care.

CR22

Sparse and contiguous indexing select for 16 bpp mode. Not supported on the

CR22

TVP3025. This bit is don’t care.

CR21

0: Cursor disable (default)

64 x 64 x 2 cursor enable. A three color cursor is not supported on the

CR21

1: Cursor enable (high)

TVP3025.

CR20

0: XGA cursor (default)

Cursor mode select

CR20

1: X-windows cursor (high)

Cursor mode select.

NOTE: The following command register 2 bits are written into the following TVP3025 indirect register bits: CR20 into

cursor-control register bit 4, CR21 into cursor-control register bit 6, CR24 into input-clock-selection register

bit 0, CR25 into multiplexer-control register 2 bit 7, CR25 into miscellaneous-control register bit 4, and CR26 into

input-clock-selection register bit 3.

2.4.15.4 Command Register 3 (RS value = 11010, when CR07 = logic 1)

Table 2–26. Command Register 3 (RS value = 11010)

BIT

NAME

VALUES

DESCRIPTION

CR37

Reserved (logic 0)

CR37

Reserved (logic 0)

CR36

Reserved (logic 0)

CR36

Reserved (logic 0)

CR35

Reserved (logic 0)

CR35

Reserved (logic 0)

CR34

Reserved (logic 0)

CR34

Reserved (logic 0)

CR33

0: Clock doubler disable

(default)

This bit enables or disables the internal 2x clock doubler circuit.

1: Clock doubler enable

CR32

Cursor select. Not supported by the TVP3025, since only 64 x 64 cursor is

CR32

allowed.

CR31,

CR31 = A9

MSBs for 10-bit address counter for cursor RAM addressing. See Section

CR30 = A8

2.4.3.

NOTE: CR33 is written into input-clock-selection register bit 4 in the BT485 mode of operation.

These registers are not initialized at power up. All command registers are set to a logic 0 when a low signal is

asserted at the RESET terminal.

TVP3025 Datasheet(PDF) 72 Page - Texas Instruments

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