TVP3025 datasheet(30/99 Pages) TI

30 / 99 page

2–16

2nd

Group

3rd

Group

4th

Group

Last Group of Pixel Data

RCLK

at Output Terminal

SYSBL

at Input Terminal

BLNK

(internal signal

before DOTCLK

pipeline delay)

PIXEL DATA

at Input Terminal

Latch Last Group of Pixel Data

and SYSBL

Latch First Group of Pixel Data

and SYSBL

LCLK

at Input Terminal

1st

Group

Figure 2–6. Frame Buffer Timing Without Using SCLK

2.3.7.4

Using the Loop Clock PLL to Generate RCLK

Many of the current high performance graphics accelerators with built in VGA support prefer to generate

their own VRAM shift clock and pixel data latching clock (LCLK) as discussed in Section 2.3.7.3. As stated

before, the TVP3025 provides an RCLK timing reference output to be used by the graphics controller to

generate these signals. A common industry problem exists, however in that the delay through the loop (i.e.,

from RCLK through the controller to produce LCLK and pixel data) may be greater than the RCLK cycle time

minus setup time. It then becomes very difficult to resynchronize the rising edges of the LCLK signal to the

reference clock (RCLK) within the specified timing requirements. The TVP3025 has incorporated a unique

loop clock PLL circuit to maintain a valid LCLK/RCLK phase relationship and ensure that proper LCLK and

pixel data setup timing is met, regardless of the amount of system loop delay.

Figure 2–7 illustrates the pixel data latching structure and the operation of the loop clock PLL. RCLK is the

internal reference clock signal which is programmed through the output-clock-selection register to be a

division of the dot clock. RCLK is very close in phase with the dot clock so that data latched on LCLK can

be synchronized to the dot clock within the device. By using the loop clock PLL to phase lock the inverted

LCLK input with the TVP3025 generated RCLK signal, an RCLK reference signal is produced that accounts

for any delay in the system.

To use the loop clock PLL to generate the RCLK signal, the RCLK divide ratio should first be programmed

in the output-clock-selection register to the appropriate divide ratio needed for the pixel data multiplexing

mode selected (see Table 2–8). Note that the divide ratio is automatically selected when the multiplex mode

is chosen in the BT485 mode of operation. Then the loop clock PLL should be programmed following the

procedure in Section 2.3.4. In general, the M and N values should be set to 1. The P value should then be

chosen such that, for the expected RCLK frequency, 110 MHz

v FVCOv 220 MHz. Finally the loop clock

PLL should be enabled for output on RCLK by setting miscellaneous-control register bit 7 to a logic 1.

TVP3025 Datasheet(PDF) 30 Page - Texas Instruments

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