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TVP3025 Datasheet(PDF) 79 Page - Texas Instruments |
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TVP3025 Datasheet(HTML) 79 Page - Texas Instruments |
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79 / 99 page  3–3 3.4 Operating Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution (each DAC) 8/6 high 8 bits Resolution (each DAC) 8/6 low 6 bits EL End-point linearity error 8/6 high 1 LSB EL y (each DAC) 8/6 low 1/4 LSB ED Differential linearity error 8/6 high 1 LSB ED y (each DAC) 8/6 low 1/4 LSB Gray scale error 5% White level relative to blank 17.69 19.05 20.4 mA White level relative to black (7.5 IRE only) 16.74 17.62 18.5 mA Black level relative to blank (7.5 IRE only) 0.95 1.44 1.9 mA Output current (see Note 3) Blank level on IOR, IOB 0 5 50 µA Output current (see Note 3) Blank level on IOG (with SYNC enabled) 6.29 7.6 8.96 mA Sync level on IOG (with SYNC enabled) 0 5 50 µA One LSB (8/6 high) 69.1 µA One LSB (8/6 low) 276.4 µA DAC-to-DAC matching 2% 5% DAC-to-DAC crosstalk –20 dB Output compliance –1 1.2 V Voltage reference output voltage 1.15 1.235 1.26 V Output impedance 50 k Ω Output capacitance f = 1 MHz, IOUT = 0 13 pF Sense voltage reference 300 350 400 mV Clock and data feedthrough –20 dB Glitch impulse (see Note 4) 50 pV–s Pipeline delay VGA port Self clocked timing 18 DOT periods Pipeline delay, VGA port Externally clocked timing 15 DOT periods Pipeline delay pixel port Self clocked timing 2 RCLK + 14 DOT periods Pipeline delay, pixel port Externally clocked timing 1 RCLK +14 DOT periods Lock time 15 ms Pixel clock PLL Lock time 15 ms Pixel clock PLL Jitter "200 ps Jitter "200 ps NOTES: 3. Test conditions for RS343-A video signals (unless otherwise specified): “Recommended Operating Conditions”, using external voltage reference Vref = 1.235 V, RSET = 523 Ω. When using the internal voltage reference, RSET may need to be adjusted in order to meet these limits. 4. Glitch impulse does not include clock and data feedthrough. The – 3-dB test bandwidth is twice the clock rate. |
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