TVP3025 datasheet(25/99 Pages) TI

25 / 99 page

2–11

2.3.5

Output Clock Selection: RCLK, SCLK, VCLK

The TVP3025 provides user-programmable reference clock (RCLK), shift clock (SCLK), and video clock

(VCLK) outputs that can be set as divisions of the dot clock. RCLK is a continuously running reference clock

that can be selected as divisions of 1, 2, 4, 8, 16, 32, or 64 of the dot clock (see Table 2–7). It is provided

as a clock reference and is typically connected back to the LCLK input to latch pixel-port data or to the

graphics controller to provide pixel data and latch timing. Since pixel-port data is latched on the rising edge

of LCLK, the RCLK frequency must be set as a function of the desired multiplexing ratio (that depends on

the pixel bus width and number of bit planes). See Section 2.3.8 and Table 2–8.

SCLK is the same as RCLK but disabled during the blank active period. SCLK is designed to be used as

the shift clock to interface directly with the VRAM. If SCLK is not used, the output can be switched off and

held low to protect against VRAM lockup due to invalid SCLK frequencies. The detailed SCLK control timing

is discussed in Section 2.3.7.1 and illustrated in Figures 2–3 through 2–5.

VCLK is a general purpose clock that can be selected as divisions of 1, 2, 4, 8, 16, 32, or 64 of the dot clock

and can also be held at logic 1 (see Table 2–7). In some systems it can used to generate graphics system

control signals (SYSBL, SYSHS, and SYSVS). In this case, it can also be used internally to latch the video

control signals into the TVP3025. The default setup is VCLK held at logic 1 since it is not used in VGA

pass-through mode.

Internally, RCLK, SCLK, and VCLK are generated from a common clock counter that is counted at the rising

edge of the pixel clock as shown in Figure 2–2. VCLK can be programmed to the opposite phase by setting

miscellaneous-control register bit 5 to logic 1. The internal clock counter is initialized any time the output-

clock-selection register is written with 3F (hex). This provides a simple mechanism to provide a known phase

relationship for the various system clocks. Therefore, when VCLK is enabled, it is naturally in phase with

RCLK and SCLK as shown in Figure 2–2.

The TVP3020 mode reset default divide ratio for RCLK is 64:1 with SCLK held at logic 0 and VCLK held

at logic 1.

When VCLK is used to latch sync and blank, some precautions must be observed when choosing certain

video timing parameters if the selected RCLK frequency is less than the selected VCLK frequency. Refer

to Appendix B for a more detailed discussion.

DOTCLK

VCLK

(DOTCLK/4 as an example)

RCLK = SCLK

(DOTCLK/2 as an example)

Figure 2–2. DOTCLK / VCLK / RCLK / SCLK Relationship

TVP3025 Datasheet(PDF) 25 Page - Texas Instruments