TVP3025 datasheet(23/99 Pages) TI

23 / 99 page

2–9

The PLLs are programmed through a group of four registers on the TVP3025 indirect register map. The

registers are listed in the following table.

INDEX

002C

PLL control register

002D

Pixel clock PLL data register

002E

MCLK PLL data register

002F

Loop clock PLL data register

Programming of the M, N, and P value registers is accomplished by writing the appropriate values to bits

0 and 1 of the PLL control register (002C) according to the following table.

BIT 1

BIT 0

N value register (7-bit)

M value register(7-bit)

P value register(post scalar, 2-bit)

Status register(read-only)

The PLL control register pointer bits above (one set for each PLL data register) are independently

auto-incremented following a write cycle to the corresponding PLL data register. Whenever bits 1 and 0 are

both written with zeros, all three sets of pointer bits are reset to zero. The current status of each pointer can

be identified by reading the PLL control register (002C) according to the following table.

PLL CONTROL

POINTER

1:0

Pixel clock PLL data register pointer

3:2

MCLK PLL data register pointer

5:4

Loop clock PLL data register pointer

Since the pointers are auto-incremented, the most efficient way to program the pixel clock PLL is to first write

zeros to bits 1 and 0 of the PLL control register, followed by three consecutive writes to the pixel clock PLL

data register to program the N, M, and P values. Following the third write, the pixel clock PLL pointer points

to the read-only status register, while the MCLK and loop clock PLL pointers point to the corresponding 7-bit

N value registers. Two more sets of three consecutive writes to the MCLK and loop clock PLL data registers

can be performed, or writes to the PLL registers can be discontinued. Note that these operations do not have

to start with the pixel clock PLL data register. The pixel clock PLL can be output on the PCLKOUT terminal

by programming the pixel clock PLL P value register bit 3 to a logic 1.

The frequency of the voltage controlled oscillator (VCO) is given by:

FVCO = FREF x ((M + 2) × 8) / (N + 2)

Provided:

FREF / (N + 2) u 0.5 MHz and

110 MHz

v (FVCO) v 220 MHz and

N, M

w 1

Then the PLL output frequency is :

FPLL = FVCO / 2P

The MCLK and DCLK outputs are further divided and controlled by the MCLK/DCLK control register as

detailed in Table 2–6.

TVP3025 Datasheet(PDF) 23 Page - Texas Instruments

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