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LPC47M192 Datasheet(PDF) 115 Page - SMSC Corporation

Part # LPC47M192
Description  LPC SUPER I/O WITH HARDWARE MONITORING BLOCK
PDF  228 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LPC47M192 Datasheet(HTML) 115 Page - SMSC Corporation

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SMSC DS – LPC47M192
Page 115
Rev. 03/30/05
DATASHEET
QFP
PIN#
DEFAULT
FUNCTION
ALT. FUNC. 1
ALT.
FUNC. 2
ALT.
FUNC. 3
DATA
REGISTER
1
DATA
REGISTER
BIT NO.
REGISTER
OFFSET
(HEX)
50
GPIO
SMI Output
7
51
GPIO
Fan Tachometer 2
0
52
GPIO
Fan Tachometer 1
1
54
GPIO
Fan Speed Control 2
2
55
GPIO
Fan Speed Control 1
3
61
Infrared Rx
GPIO
4
62
Infrared Tx
GPIO
5
63
GPIO
Keyboard Reset
6
64
GPIO
Gate A20
GP3
7
4D
1
GPIO
Drive Density Select 0
0
2
GPIO
Drive Density Select 1
EETI
1
17
GPIO
Power Management
Event
2
28
GPIO
Device Disable Reg.
Control
EETI
3
N/A
Reserved
GP4
7:4
4E
92
GPIO
Ring Indicator 2
0
94
GPIO
Data Carrier Detect 2
1
95
GPIO
Receive Serial Data 2
2
96
GPIO
Transmit Serial Data 2
3
97
GPIO
Data Set Ready 2
4
98
GPIO
Request to Send 2
5
99
GPIO
Clear to Send 2
6
100
GPIO
Date Terminal Ready
GP5
7
4F
48
GPIO
LED
EETI
0
49
GPIO
LED
EETI
1
N/A
Reserved
GP6
7:2
50
Note 1:
The GPIO Data and Configuration Registers are located in PME block at the offset shown from
the
PME_BLK address.
7.12.3 GPIO CONTROL
Each GPIO port has an 8-bit control register that controls the behavior of the pin. These registers are defined in the
“Runtime Registers” section of this specification.
Each GPIO port may be configured as either an input or an output. If the pin is configured as an output, it can be
programmed as open-drain or push-pull. Inputs and outputs can be configured as non-inverting or inverting. Bit[0] of
each GPIO Configuration Register determines the port direction, bit[1] determines the signal polarity, and bit[7]
detemines the output driver type select. The GPIO configuration register Output Type select bit[7] applies to GPIO
functions and the nSMI Alternate functions.
The Polarity Bit (bit 1) of the GPIO control registers control the GPIO pin when the pin is configured for the GPIO
function and when the pin is configured for the alternate function for all pins, with the exception of the DDRC function
on GP43, the analog game port pins (J1X, J1Y, J2X, J2Y) and the either edge triggered interrupts. When the
alternate function is selected for the analog joystick pins (GP14, GP15, GP16 and GP17), these pins become open
drain, non-inverted outputs.
The basic GPIO configuration options are summarized in Table 54.
Table 54 - GPIO Configuration Summary
SELECTED
FUNCTION
DIRECTION
BIT
POLARITY
BIT
DESCRIPTION
B0
B1
0
0
Pin is a non-inverted output.
0
1
Pin is an inverted output.
1
0
Pin is a non-inverted input.
GPIO
1
1
Pin is an inverted input.



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