LPC47M192 datasheet(114/228 Pages) SMSC

114 / 228 page

SMSC DS – LPC47M192

Page 114

Rev. 03/30/05

DATASHEET

GPIO PIN

GPIO REGISTER

PIN#

PIN NAME

(Default Func/

Alternate Funcs)

PWR

WELL

PCI

RESET

VCC

POR

VTR

POR

REG

OFFS

(hex)

REG

PCI

RESET

VCC

POR

VTR

POR

SOFT

RESET

SMI/PME

NOTES

GP43/DDRC

VCC

GP43

Note 5

Note

0x01

SMI/PME

1, 5

GP50/nRI2

VCC

GP50

0x01

PME

GP51/nDCD2

VCC

GP51

0x01

PME

GP52/RXD2(IRRX)

VCC

GP52

0x01

PME

GP53/TXD2 (IRTX)

VTR

Out – low

Out–

low

Out–

low

GP53

0x00

PME

1, 3

GP54/nDSR2

VCC

GP54

0x01

SMI/PME

GP55/nRTS2

VCC

GP55

0x01

SMI/PME

GP56/nCTS2

VCC

GP56

0x01

SMI/PME

100

GP57/nDTR2

VCC

GP57

0x01

SMI/PME

GP60/LED1

VTR

GP60

0x01

SMI/PME

GP61/LED2

VTR

GP61

0x01

SMI/PME

Note 1:

These pins are inputs to VCC and VTR powered logic.

Note 2:

The fan control pins (FAN1 and FAN2) come up as outputs and low following a VCC POR and PCI Reset.

Note 3:

The IRTX pins (IRTX2/GP35 and GP53/TXD2(IRTX)) are driven low when the part is powered by VTR

(VCC=0V with VTR=3.3V). These pins will remain low following a VCC POR until IRTX function is selected

by setting the activate bit, at which time the pin will reflect the state of the transmit output of the IR block. It

will remain low following a VCC POR until GPIO input function is selected, at which time the pin will reflect

the state of the GPIO data bit. The GP53/TXD2 (IRTX) pin will remain low following a VCC POR (in

addition to conditions stated above) until serial port 2 is enabled by setting the activate bit, at which time

the pin will reflect the state of the transmit output of the Serial Port 2 block.

Note 4:

These pins are inputs to VCC powered logic.

Note 5:

Bits [3:2] (Alternate Function Select bits) of this register are reset (cleared) on VCC POR and PCI Reset

(and VTR POR).

7.12.2 DESCRIPTION

Each GPIO port has a 1-bit data register and an 8-bit configuration control register. The data register for each GPIO

port is represented as a bit in one of the 8-bit GPIO DATA Registers, GP1 to GP6. The bits in these registers reflect

the value of the associated GPIO pin as follows. Pin is an input: The bit is the value of the GPIO pin. Pin is an

output: The value written to the bit goes to the GPIO pin. Latched on read and write. All of the GPIO registers are

located in the PME block see “Run Time Register” section. The GPIO ports with their alternate functions and

configuration state register addresses are listed in Table 53.

Table 53 - General Purpose I/O Port Assignments

QFP

PIN#

DEFAULT

FUNCTION

ALT. FUNC. 1

ALT.

FUNC. 2

ALT.

FUNC. 3

DATA

BIT NO.

OFFSET

(HEX)

GPIO

Joystick 1 Button 1

GPIO

Joystick 1 Button 2

GPIO

Joystick 2 Button 1

GPIO

Joystick 2 Button 2

GPIO

Joystick 1 X-Axis

GPIO

Joystick 1 Y-Axis

GPIO

Joystick 2 X-Axis

GPIO

Joystick 2 Y-Axis

GP1

GPIO

P17

GPIO

P16

EETI

GPIO

P12

EETI

N/A

Reserved

GPIO

(System

Option)

GPIO

MIDI_IN

GPIO

MIDI_OUT

GP2

LPC47M192 Datasheet(PDF) 114 Page - SMSC Corporation

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