LPC47M192 datasheet(118/228 Pages) SMSC

118 / 228 page

SMSC DS – LPC47M192

Page 118

Rev. 03/30/05

DATASHEET

Note 2

: GP36-GP37 and GP40 should not be connected to any VTR powered external circuitry. These

pins are not used for wakeup.

Note 3

: GP60 and GP61 have LED functionality which must be active under VTR so its buffer is

Note 4

: These pins can be used for wakeup events to generate a PME while the part is under VTR power

(VCC=0).

Note 5

: These pins cannot be used for wakeup events to generate a PME while the part is under VTR power

(VCC=0). The GP32, GP33 and GP53 pins come up as output and low on a VCC POR and PCI reset.

Note 6

: GP43 defaults to the GPIO function on VCC POR and PCI Reset.

7.12.6 EITHER EDGE TRIGGERED INTERRUPTS

Six GPIO pins are implemented such that they allow an interrupt (PME or SMI) to be generated on both a high-to-low

and a low-to-high edge transition, instead of one or the other as selected by the polarity bit.

The either edge triggered interrupts (EETI) function as follows: If the EETI function is selected for the GPIO pin, then

the bits that control input/output, polarity and open drain/push-pull have no effect on the function of the pin. However,

the polarity bit does affect the value of the GP bit (i.e., register GP2, bit 2 for GP22).

A PME or SMI interrupt occurs if the PME or SMI enable bit is set for the corresponding GPIO and the EETI function

is selected on the GPIO. The PME or SMI status bits are set when the EETI pin transitions (on either edge) and are

cleared on a write of ‘1’. There are also status bits for the EETIs located in the MSC_STS register, which are also

cleared on a write of ‘1’. The MSC_STS register provides the status of all of the EETI interrupts within one register.

The PME, SMI or MSC status is valid whether or not the interrupt is enabled and whether or not the EETI function is

selected for the pin.

Miscellaneous Status Register (MSC_STS) is for the either edge triggered interrupt status bits. If the EETI function is

selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding MSC status bits.

Status bits are cleared on a write of ‘1’. See the “Runtime Registers” section for more information.

The configuration register for the either edge triggered interrupt status bits is defined in the “Runtime Registers”

section.

7.12.7 LED FUNCTIONALITY

The LPC47M192 provides LED functionality on two GPIOs, GP60 and GP61. These pins can be configured to turn

the LED on and off and blink independent of each other through the LED1 and LED2 runtime registers at offset 0x5D

and 0x5E from the base address located in the primary base I/O address in Logical Device A.

The LED pins (GP60 and GP61) are able to control the LED while the part is under VTR power with VCC removed.

In order to control a LED while the part is under VTR power, the GPIO pin must be configured for the LED function

and either open drain or push-pull buffer type. In the case of open-drain buffer type, the pin is capable of sinking

current to control the LED. In the case of push-pull buffer type, the part will source current. The part is also able to

blink the LED under VTR power. The LED will not blink under VTR power (VCC removed) if the external 32kHz clock

is not connected.

The LED pins can drive a LED when the buffer type is configured to be push-pull and the part is powered by either

VCC or VTR, since the buffers for these pins are powered by VTR. This means they will source their specified current

from VTR even when VCC is present.

The LED control registers are defined in the “Runtime Register” section.

7.13 SYSTEM MANAGEMENT INTERRUPT (SMI)

The LPC47M192 implements a “group” nIO_SMI output pin. The System Management Interrupt is a non-maskable

interrupt with the highest priority level used for OS transparent power management. The nSMI group interrupt output

consists of the enabled interrupts from each of the functional blocks in the chip and many of the GPIOs and the Fan

tachometer pins. The GP27/nIO_SMI pin, when selected for the nIO_SMI function, can be programmed to be active

high or active low via the polarity bit in the GP27 register. The output buffer type of the pin can be programmed to be

open-drain or push-pull via bit 7 of the GP27 register. The nIO_SMI pin function defaults to active low, open-drain

output.

The interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1 to 5. The nSMI output is then

enabled onto the group nIO_SMI output pin via bit[7] in the SMI Enable Register 2. The SMI output can also be

LPC47M192 Datasheet(PDF) 118 Page - SMSC Corporation

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