LPC47M192 datasheet(120/228 Pages) SMSC

120 / 228 page

SMSC DS – LPC47M192

Page 120

Rev. 03/30/05

DATASHEET

For the GPIO events, the polarity of the edge used to set the status bit and generate a PME is controlled by the

polairty bit of the GPIO control register. For non-inverted polarity (default) the status bit is set on the low-to-high

edge. If the EETI function is selected for a GPIO then both a high-to-low and a low-to-high edge will set the

corresponding PME status bits. Status bits are cleared on a write of ‘1’.

The PME Wake registers also include status and enable bits for the fan tachometer input.

See the “Keyboard and Mouse PME Generation” section for information about using the keyboard and mouse signals

to generate a PME.

In the LPC47M192 the nIO_PME pin can be programmed to be an open drain, active low, driver. The LPC47M192

nIO_PME pin is fully isolated from other external devices that might pull the nIO_PME signal low; i.e., the nIO_PME

signal is capable of being driven high externally by another active device or pullup even when the LPC47M192 VCC

is grounded, providing VTR power is active. The LPC47M192 nIO_PME driver sinks 6mA at .55V max (see section

4.2.1.1 DC Specifications, page 122, in the “PCI Local Bus Specification,” revision 2.1).

The PME registers are run-time registers as follows. These registers are located in system I/O space at an offset

from PME_BLK, the address programmed in Logical Device A at registers 0x60 and 0x61.

The following registers are for GPIO wakeup events:

PME Wake Status 2 (PME_STS2), PME Wake Enable 2 (PME_EN2)

PME Wake Status 3 (PME_STS3), PME Wake Enable 3 (PME_EN3)

PME Wake Status 4 (PME_STS4), PME Wake Enable 4 (PME_EN4)

PME Wake Status 5 (PME_STS5), PME Wake Enable 5 (PME_EN5)

See PME register description in the “Runtime Registers” Section.

Enabling SMI Events onto the PME Pin

There is a bit in the PME Status Register 3 to show the status of the internal “group” SMI signal in the PME logic (if bit

5 of the SMI_EN2 register is set). This bit, DEVINT_STS, is at bit 3 of the PME_STS3 register. This bit is defined as

follows:

0=The group SMI output is inactive.

1 = The group SMI output is active.

Note:

Bit 5 of the SMI_EN2 register must also be set. This bit is cleared on a write of ‘1’.

There is a bit in the PME Enable Register 3 to enable the SMI onto the nIO_PME pin (if the nIO_PME function is

selected for GP42). This bit, DEVINT_EN, is at bit 3 of the PME_EN3 register. This bit will enable the internal “group”

SMI signal (if bit 5 of the SMI_EN2 register is set) into the PME logic through the DEVINT_STS bit as follows: If the

DEVINT_EN bit is ‘1’ and the DEVINT_STS bit is ‘1’ then the nIO_PME pin will be active. This pin has its polarity

controlled by the polarity bit in the GP42 register.

This bit is defined as follows:

0 = Disable group SMI output from the nIO_PME pin.

1 = Enable group SMI output onto the nIO_PME pin. That is, if this bit is set and the DEVINT_STS bit is set

then a nPME is generated.

Note:

Bit 5 of the SMI_EN2 register must also be set.

7.14.1 ‘WAKE ON SPECIFIC KEY’ OPTION

The LPC47M192 has logic to detect a single keyboard scan code for wakeup (PME generation). The scan code is

programmed onto the Keyboard Scan Code Register, a runtime register at offset 0x5F from the base address located

in the primary base I/O address in Logical Device A. This register is powered by VTR and reset on VTR POR.

The PME status bit for this event is located in the PME_STS1 register at bit 5 and the PME enable bit for this event is

located in the PME_EN1 register at bit 5. See the “Runtime Registers” section for a definition of these registers.

Data transmissions from the keyboard consist of an 11-bit serial data stream. A logic 1 is sent at an active high level.

The following table shows the functions of the bits.

LPC47M192 Datasheet(PDF) 120 Page - SMSC Corporation

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