LPC47M192 datasheet(121/228 Pages) SMSC

121 / 228 page

SMSC DS – LPC47M192

Page 121

Rev. 03/30/05

DATASHEET

Bit

Function

Start bit (always 0)

Data bit 0 (least significant bit)

Data bit 1

Data bit 2

Data bit 3

Data bit 4

Data bit 5

Data bit 6

Data bit 7 (most significant bit)

Parity bit (odd parity)

Stop Bit (always 1)

The timing for the keyboard clock and data signals are shown in the “Timing Diagrams” section.

The process to find a match for the scan code stored in the Keyboard Scan Code register is as follows:

Begin sampling the data at the first falling edge of the keyboard clock following a period where the clock line has

been high for 115-145usec. The data at this first clock edge is the start bit. The first data bit follows the start bit (clock

2). Sample the data on each falling edge of the clock. Store the eight bits following the stop bit to compare with the

scan code stored in the Keyboard Scan Code register. Sample the comparator within 100usec of the falling edge of

clock 9 (for example, at clock 10).

Sample the parity bit and check that the 8 data bits plus the parity bit always have an odd number of 1’s (odd parity).

Repeat until a match is found. If the 8 data bits match the scan code stored in the Keyboard Scan Code register and

the parity is correct, then it is considered a match. When a match is found and if the stop bit is 1, set the event status

bit (bit 5 of the PME_STS1 register) to ‘1’ within 100usec of the falling edge of clock 10.

The state machine will reset after 11 clocks and the process will restart. The process will continue until it is shut off by

setting the SPEKEY_EN bit (see following sub-section).

The state machine will reset if there is a period where the clock remains high for more than one keyboard clock

period (115-145usec) in the middle of the transmission (i.e., before clock 11). This is to prevent the generation of a

false PME.

The SPEKEY_EN bit at bit 1 of the CLOCKI32 register at 0xF0 in Logical Device A is used to control the “wake-on-

specific feature. This bit is used to turn the logic for this feature on and off. It will disable the 32kHz clock input to the

logic. The logic will draw no power when disabled. The bit is defined as follows:

0= “Wake on specific key” logic is on (default)

1= “Wake on specific key” logic is off

Note:

The generation of a PME for this event is controlled by the PME enable bit (located in the PME_EN1 register

at bit 5) when the logic for feature is turned on.

7.15 FAN SPEED CONTROL AND MONITORING

The LPC47M192 can control the speed of two separate fans as well as monitor them if they are equipped with fan

tachometer outputs. The following sections will clarify how this chip controls the speed of a fan and its’ monitoring

capabilities.

7.15.1 FAN SPEED CONTROL

The fan speed control for the LPC47M192 is implemented as pulse width modulators with fan clock speed selection.

There are two pins, FAN1 and FAN2 (pins 55 and 54 respectively), that can control the speed of two separate fans.

These signals are controlled by the Runtime registers FANx and Fan Control that are described below (see also

section 8

− RUNTIME REGISTERS).

Note:

These fan control pins come up as outputs and are low following a VCC POR and PCI Reset. These pins may

not be used for wakeup events under VTR power (VCC=0).

LPC47M192 Datasheet(PDF) 121 Page - SMSC Corporation

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