LPC47M192 datasheet(125/228 Pages) SMSC

125 / 228 page

SMSC DS – LPC47M192

Page 125

Rev. 03/30/05

DATASHEET

in a value for Term 1 in Equation 1 of 111.70 (~112) for a 4400 RPM. The following tables show examples of the

desired functionality.

Note:

All calculations of Count were based on tachometer inputs with two pulses per revolution and on the clock

source input divided down by two (default settings).

RPM

Time per

Revolution

Term 1 for “Divide by 2”

(Default) in Decimal

Preload

Count =

(Term 1) + Preload

Comments

4400

13.64 ms

112 counts

144

Typical RPM

3080

19.48 ms

160 counts

192

70% RPM

2640

22.73 ms

186 counts

218

60% RPM

2204

27.22 ms

223 counts

255

(maximum count)

50% RPM

The divisor for each fan is programmable via the Fan Control Register, Logical Device A, runtime register 0x58. The

choices for the divisor are 1, 2, 4 and 8. The default value is 2.

Mode Select

Nominal

RPM

Time per

Revolution

Preload

Counts for the

Given Speed in

Decimal

70% RPM

Time per

Revolution for

70% RPM

Divide by 1

8800

6.82 ms

144

6160

9.74 ms

Divide by 2

4400

13.64 ms

144

3080

19.48 ms

Divide by 4

2200

27.27 ms

144

1540

38.96 ms

Divide by 8

1100

54.54 ms

144

770

77.92 ms

7.16 SECURITY FEATURE

The following register describes the functionality to support security in the LPC47M192.

7.16.1 GPIO DEVICE DISABLE REGISTER CONTROL

The GPIO pin GP43 is used for the Device Disable Register Control (DDRC) function. Setting bits[3:2] of the GP43

configuration register to ‘01’, selects the DDRC function for the GP43 pin. When bits[3:2]=01 the GP43 pin is an

input, with non-inverted polarity. Bits[3:2] cannot be cleared by writing to these bits; they are cleared by VTR POR,

VCC POR and PCI Reset. That is, when the DDRC function is selected for this pin, it cannot be changed, except by a

VCC POR, PCI reset or VTR POR.

When the DDRC function is selected for GP43, the Device Disable register is controlled by the value of the GP43 pin

as follows:

If the GP43 pin is high, the Device Disable Register is Read-Only.

If the GP43 pin is low, the Device Disable Register is Read/Write.

7.16.2 DEVICE DISABLE REGISTER

The Device Disable Register is located in the PME register block at offset 0x22 from the PME_BLK base I/O address

in logical device A. Writes to this register are blocked when the GP43 pin is configured for the Device Disable

The configuration register for the device disable register is defined in the “Runtime Registers” section.

7.17 GAME PORT LOGIC

The LPC47M192 implements logic to support a dual game port. This logic includes the following for each game port:

two 555 timers, two game port RC constant inputs (x-axis and y-axis), two game port button inputs and game port

interface logic. The implementation of the Game Port uses a simple A/D converter constructed from a 555 timer to

digitize the analog value of a potentiometer for the x-axis and y-axis of the joystick.

LPC47M192 Datasheet(PDF) 125 Page - SMSC Corporation

LPC47M192 Datasheet(HTML) 125 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL