LPC47M192 datasheet(129/228 Pages) SMSC

129 / 228 page

SMSC DS – LPC47M192

Page 129

Rev. 03/30/05

DATASHEET

7.18 Hardware Monitoring Interface

The Hardware Monitoring Block is a standalone block in the 2. It can be accessed using SMBus interface. This block

is used to monitor +1.5, +1.8, +2.5V, +3.3V, +5V, +12V and Vccp (core processor) voltages. It can also monitor its

own internal HVCC or HVSB. The block can be used to measure internal temperature and two external temperatures

and diode faults. It can indicate out-of-limit temperature and voltage conditions. The block has an ability to output

20ms low pulse.

7.18.1 HARDWARE MONITORING INTERFACE SIGNAL DEFINITION

The following table shows the pins required for the Hardware Monitoring Block.

PIN NAME

TYPE

DESCRIPTION

SDA

Digital I/O

(Open Drain)

System Management Bus bi-directional Data.

Open Drain

output.

SCLK

Digital Input

System Management Bus Clock.

HVSS

Analog Ground

Internally connected to all of the Hardware Monitoring Block

circuitry.

HVCC

Power

+3.3V VCC pin dedicated to the Hardware Monitoring block.

Can be powered by +3.3V Standby power if monitoring in low

power states is required.

VID0

Digital Input

Voltage supply readout from the processor. This value is read

in the VID Register.

VID1

Digital Input

Voltage supply readout from the processor. This value is read

in the VID Register.

VID2

Digital Input

Voltage supply readout from the processor. This value is read

in the VID Register.

VID3

Digital Input

Voltage supply readout from the processor. This value is read

in the VID Register.

D0-/XNOR_IN

Analog Input/

Digital Input

This is the negative input (current sink) from the remote

thermal diode. This serves as the negative input into the A/D.

If held high at power-up, initiates XNOR chain test mode.

D0+

Analog Input

This is the positive input (current source) from the remote

thermal diode. This serves as the positive input into the A/D.

D1-

Analog Input

See D0- pin description.

D1+

Analog Input

See D0+ description.

12V_IN/VID4

Analog

Input/

Digital Input

Defaults to Analog Input for +12V. Optionally, can be

configured to read the VID4 pin, a voltage supply readout from

the processor. This value is read in the VID4 Register.

+5V_IN

Analog Input

Analog input for +5V

+3.3V_IN

Analog Input

Analog input for +3.3V

+2.5V_IN

Analog Input

Analog input for +2.5V

+1.8V_IN

Analog Input

Analog input for +1.8V

+1.5V_IN

Analog Input

Analog input for +1.5V

+Vccp_IN

Analog Input

Analog input for +Vccp (processor voltage: 0 to 3.0V).

A0/RESET#/

THERM#/XNOR_OUT

Digital I/O

(Open Drain)

The lowest order programmable bit of the SMBus Address.

Can also be configured to be a minimum 20msec low Reset

output pulse, or as an interrupt output for temperature and

voltage interrupts. This pin functions as an output when the

Hardware Monitor Block is in XNOR-Chain test mode.

7.18.2 SMBUS INTERFACE

The host processor communicates with the Hardware Monitor Block through a series of read/write registers via the

SMBus interface. SMBus is a serial communication protocol between a computer host and its peripheral devices.

The SMBus protocol includes a physical layer based on the I

2CTM serial bus.

LPC47M192 Datasheet(PDF) 129 Page - SMSC Corporation

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