LPC47M192 datasheet(132/228 Pages) SMSC

132 / 228 page

SMSC DS – LPC47M192

Page 132

Rev. 03/30/05

DATASHEET

7.18.2.1.5

Slave Device Time-Out

The device will not time-out when SCLK is held low longer than TTIME-OUT Min = 25ms.

7.18.2.1.6

Stretching the SCLK Signal

The Hardware Monitor Block supports stretching of the SCLK by other devices on the SMBus. The Hardware Monitor

Block does not stretch the SCLK.

7.18.2.1.7

SMBus Timing

The SMBus Slave Interface complies with the SMBus AC Timing Specification. See the SMBus timing in the “Timing

Diagram” section.

7.18.2.1.8

Bus Reset Sequence

The SMBus Slave Interface will reset and return to the idle state upon a START field followed immediately by a STOP

field.

7.18.2.1.9

SMBus Alert Response Address

The Hardware Monitor Block implements the SMBALERT# signal. The THERM# interrupt pin can be used as the

SMBALERT#. SMBALERT# is used in conjunction with the SMBus General Call Address, 0001 100.

The Hardware Monitor Block device can signal the host that it wants to talk by pulling the SMBALERT# low. The host

processes the interrupt and simultaneously accesses all SMBALERT# devices through a modified Receive Byte

operation with the Alert Response Address (ARA). The Hardware Monitor Block, which pulled SMBALERT# low, will

acknowledge the Alert Response Address and respond with its device address.

The host performs a modified Receive Byte operation with the alert response address. The 7-bit device address

provided by the Hardware Monitor Block device is placed in the 7 most significant bits of the byte. The eighth bit can

be a zero or one.

Table 61 - Modified SMBus Receive Byte Protocol Response to ARA

FIELD:

START

ALERT

RESPONSE

ADDRESS

ACK

HW MONITOR

BLOCK SLAVE

ADDRESS

NACK

STOP

Bits:

After acknowledging the slave address, the Hardware Monitor Block must disengage its SMBALERT# pulldown. If the

condition that caused the interrupt remains, the Hardware Monitor Block will reassert the SMBALERT# on the next

monitoring cycle.

7.18.3 HARDWARE MONITORING BLOCK

The following sub-sections describe the Hardware Monitoring Block.

7.18.3.1

Input Monitoring

The Hardware Monitor Block’s monitoring function is started by writing a ‘1’ to the START bit in the Configuration

These values can be compared to the programmed limits in the Limit Register via SMBus interface. The out-of-limit

and diode fault conditions are stored in the Interrupt Status Registers.

7.18.3.2

Resetting the Hardware Monitoring Block

7.18.3.2.1

Power On Reset

All the registers in the Hardware Monitor Block reset to a default value when power is applied to the block. The

default state of the register is shown in the table in the Register Summary subsection. The default state of Value or

Limit Registers are not shown because these registers have indeterminate power on values. Usually the first action

after power up is to write limits into the Limit Registers.

LPC47M192 Datasheet(PDF) 132 Page - SMSC Corporation

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