LPC47M192 datasheet(131/228 Pages) SMSC

131 / 228 page

SMSC DS – LPC47M192

Page 131

Rev. 03/30/05

DATASHEET

Table 58 - SMBus Read Byte Protocol

FIELD:

START

SLAVE

ADDR

ACK

REG.

ADDR

ACK START

SLAVE

ADDR

RD ACK

REG.

DATA

NACK

STOP

Bits:

Send Byte

The Send Byte protocol is used to set the Internal Address Register to the correct register in the Hardware Monitor

Block. No data is transferred for a Send Byte protocol. The Send Byte can be followed by the Receive Byte protocol

described below in order to read data from the register. The send byte protocol cannot be used to write data - if data

is to be written to a register then the write byte protocol must be used as described in subsection above. The send

byte protocol is shown in the table below.

Table 59 - SMBus Send Byte Protocol

FIELD:

START

SLAVE

ADDR

ACK

REG.

ADDR

ACK

STOP

Bits:

Receive Byte

The Receive Byte protocol is used to read data from the registers when the register address is known to be at the

desired address (using the Internal Address Register). This is used when the register address has been written to

the desired address using the Send Byte protocol. This can be used for successive reads of the same register. The

data will only be read if the protocol shown in Table 4 is performed correctly. Only one byte is transferred at time for

a Receive Byte protocol.

Table 60 - SMBus Receive Byte Protocol

FIELD: START

SLAVE

ADDR

ACK

REG.

DATA

NACK

STOP

Bits:

7.18.2.1.2

Slave Address

The slave address is the unique address for the Hardware Monitor Block that identifies the device on SMBus.

The Hardware Monitor Block’s slave address is determined by the level on the A0 pin. The level on this pin forms the

LSB of the 7-bit address 0101_10x. This pin may be used to support up to 2 Hardware Monitor Blocks in a given

system.

The upper 6 bits of the Hardware Monitor Block’s slave address are hardwired in the Hardware Monitor Block.

7.18.2.1.3

Invalid Protocol Response Behavior

Registers that are accessed with an invalid protocol will not be updated. A register will only be updated following a

valid protocol. The only valid protocols are the read byte, receive byte and write byte protocols described above.

The only valid slave address is determined by the level on the A0 pin as the LSB of the address 0101_10x.

The only valid registers for a read or write protocol are the registers shown in the Registers Section. Reserved

registers are not considered valid registers.

Attempting to communicate with the Hardware Monitor Block over SMBus with an invalid slave address, invalid

state.

7.18.2.1.4

General Call Address Response

The Hardware Monitor Block will not respond to a general call address of 0000_000.

LPC47M192 Datasheet(PDF) 131 Page - SMSC Corporation

LPC47M192 Datasheet(HTML) 131 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL