LPC47M192 datasheet(116/228 Pages) SMSC

116 / 228 page

SMSC DS – LPC47M192

Page 116

Rev. 03/30/05

DATASHEET

7.12.4 GPIO OPERATION

GPIO

Data Register

Bit-n

SD-bit

GPx_nIOR

GPIO

Configuration

(Polarity)

GPIO

Configuration

(Input/Output)

D-TYPE

Transparent

GPx_nIOW

FIGURE 7 - GPIO FUNCTION ILLUSTRATION

The operation of the GPIO ports is illustrated in FIGURE 7.

Note:

FIGURE 7 is for illustration purposes only and is not intended to suggest specific implementation details.

When the following functions are selected, the associated GPIO pins have bi-directional functionality:

P12, P16, P17 and game port x-axis and y-axis inputs (J1X, J1Y, J2X, J2Y).

When a GPIO port is programmed as an input, reading it through the GPIO data register latches either the inverted or

non-inverted logic value present at the GPIO pin. Writing to a GPIO port that is programmed as an input has no

effect (Table 55)

When a GPIO port is programmed as an output, the logic value or the inverted logic value that has been written into

the GPIO data register is output to the GPIO pin. Reading from a GPIO port that is programmed as an output returns

the last value written to the data register (Table 55). When the GPIO is programmed as an output, the pin is

excluded from the PME and SMI logic.

Table 55 – GPIO Read/Write Behavior

HOST OPERATION

GPIO INPUT PORT

GPIO OUTPUT PORT

READ

LATCHED VALUE OF GPIO PIN

LAST WRITE TO GPIO DATA REGISTER

WRITE

NO EFFECT

BIT PLACED IN GPIO DATA REGISTER

The LPC47M192 provides 31 GPIOs that can directly generate a PME. See the table in the next section. The

polarity bit in the GPIO control registers select the edge on these GPIO pins that will set the associated status bit in

the PME_STS 2 register. The default is the low-to-high edge. If the corresponding enable bit in the PME_EN 2

the PME_BLK of runtime registers which are located at the address contained in the configuration registers 0x60 and

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