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LPC47M192 Datasheet(PDF) 113 Page - SMSC Corporation

Part # LPC47M192
Description  LPC SUPER I/O WITH HARDWARE MONITORING BLOCK
PDF  228 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LPC47M192 Datasheet(HTML) 113 Page - SMSC Corporation

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SMSC DS – LPC47M192
Page 113
Rev. 03/30/05
DATASHEET
events are enabled. Note that the keyboard and mouse isolation bits only prevent the internal 8042 in the part from
setting these status bits.
Case 1: Keyboard and/or Mouse Powered by VTR
The KBD and/or MOUSE status bits will be set upon a VTR POR if the keyboard and/or mouse are powered by VTR.
In this case, an IO_PME# will not be generated, since the keyboard and mouse PME enable bits are reset to zero on
a VTR POR. The BIOS software needs to clear these PME status bits after power-up.
Case 2: Keyboard and/or Mouse Powered by VCC
The KBD and/or MOUSE status bits will be set upon a VCC POR if the keyboard and/or mouse are powered by VCC.
In this case, an IO_PME# will be generated if the enable bits were set for wakeup, since the keyboard and mouse
PME enable bits are VTR powered. Therefore, if the keyboard and mouse are powered by VCC, the enable bits for
keyboard and mouse events should be cleared prior to entering a sleep state where VCC is removed (i.e., S3) to
prevent a false PME from being generated. In this case, the keyboard and mouse should only be used as PME
and/or wake events from the S0 and/or S1 states. The BIOS software needs to clear these PME status bits after
power-up.
7.12 GENERAL PURPOSE I/O
The LPC47M192 provides a set of flexible Input/Output control functions to the system designer through the 37
independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and many of
them can be individually enabled to generate an SMI and a PME.
7.12.1 GPIO PINS
The following pins include GPIO functionality. These pins are defined in the table below. All GPIOs default to the
GPIO function except for GP34 and GP35 which default to IRRX2 and IRTX2.
GPIO PIN
GPIO REGISTER
PIN#
PIN NAME
(Default Func/
Alternate Funcs)
PWR
WELL
PCI
RESET
VCC
POR
VTR
POR
REG
OFFS
ET
(hex)
REG
PCI
RESET
VCC
POR
VTR
POR
SOFT
RESET
SMI/PME
NOTES
32
GP10/J1B1
VCC
-
-
In
23
GP10
-
-
0x01
-
PME
1
33
GP11/J1B2
VCC
-
-
In
24
GP11
-
-
0x01
-
PME
1
34
GP12 /J2B1
VCC
-
-
In
25
GP12
-
-
0x01
-
PME
1
35
GP13 /J2B2
VCC
-
-
In
26
GP13
-
-
0x01
-
PME
1
36
GP14 /J1X
VCC
-
-
In
27
GP14
-
-
0x01
-
PME
1
37
GP15 /J1Y
VCC
-
-
In
28
GP15
-
-
0x01
-
PME
1
38
GP16 /J2X
VCC
-
-
In
29
GP16
-
-
0x01
-
PME
1
39
GP17 /J2Y
VCC
-
-
In
2A
GP17
-
-
0x01
-
PME
1
41
GP20/P17
VCC
-
-
In
2B
GP20
-
-
0x01
-
SMI/PME
1
42
GP21/P16/nDS1
VCC
-
-
In
2C
GP21
-
-
0x01
-
SMI/PME
1
43
GP22/P12/nMTR1
VCC
-
-
In
2D
GP22
-
-
0x01
-
SMI/PME
1
45
GP24/SYSOPT
VCC
-
-
In
2F
GP24
-
-
0x01
-
SMI/PME
1
46
GP25/MIDI_IN
VCC
-
-
In
30
GP25
-
-
0x01
-
SMI/PME
1
47
GP26/MIDI_OUT
VCC
-
-
In
31
GP26
-
-
0x01
-
SMI/PME
1
50
GP27/nIO_SMI
VCC
-
-
In
32
GP27
-
-
0x01
-
nIO_SMI/PME
1
51
GP30/FAN_TACH2
VCC
-
-
In
33
GP30
-
-
0x01
-
SMI/PME
1
52
GP31/FAN_TACH1
VCC
-
-
In
34
GP31
-
-
0x01
-
SMI/PME
1
54
GP32/FAN2
VCC
Out – low
Out–
low
In
35
GP32
0x00
0x00
0x01
-
SMI/PME
1, 2
55
GP33/FAN1
VCC
Out – low
Out–
low
In
36
GP33
0x00
0x00
0x01
-
SMI/PME
1, 2
61
IRRX2/GP34
VCC
-
-
In
37
GP34
-
-
0x05
-
SMI
62
IRTX2/GP35
VTR
Out – low
Out–
low
Out -
low
38
GP35
0x04
0x04
0x04
-
-
3, 4
63
GP36/nKBDRST
VCC
-
-
In
39
GP36
-
-
0x01
-
-
64
GP37/A20M
VCC
-
-
In
3A
GP37
-
-
0x01
-
-
1
GP40/DRVDEN0
VCC
-
-
In
3B
GP40
-
-
0x01
-
-
2
GP41/DRVDEN1
VCC
-
-
In
3C
GP41
-
-
0x01
-
SMI/PME
1
17
GP42/nIO_PME
VTR
-
-
In
3D
GP42
-
-
0x01
-
SMI/nIO_PME



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