LPC47M192 datasheet(109/228 Pages) SMSC

109 / 228 page

SMSC DS – LPC47M192

Page 109

Rev. 03/30/05

DATASHEET

7.11.8 DEFAULT RESET CONDITIONS

The LPC47M192 has one source of hardware reset: an external reset via the PCI_RESET# pin. Refer to Table 52 for

the effect of each type of reset on the internal registers.

Table 52 - Resets

DESCRIPTION

HARDWARE RESET

(PCI_RESET#)

KCLK

Low

KDAT

Low

MCLK

Low

MDAT

Low

Host I/F Data Reg

N/A

Host I/F Status Reg

00H

N/A: Not Applicable

GATEA20 AND KEYBOARD RESET

The LPC47M192 provides two options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and

KRESET and Port 92 Fast GateA20 and KRESET.

PORT 92 FAST GATEA20 AND KEYBOARD RESET

Port 92 Register

This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register (Logical

Device 7, 0xF0) set to 1.

This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions.

Name

Port 92

Location

92h

Default Value

24h

Attribute

Read/Write

Size

8 bits

PORT 92 REGISTER

BIT

FUNCTION

7:6

Reserved. Returns 00 when read

Reserved. Returns a 1 when read

Reserved. Returns a 0 when read

Reserved. Returns a 1 when read

ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be

driven low. Writing a 1 to this bit causes the ALT_A20 signal to be driven high.

Alternate System Reset. This read/write bit provides an alternate system reset

function. This function provides an alternate means to reset the system CPU to

effect a mode switch from Protected Virtual Address Mode to the Real Address

Mode. This provides a faster means of reset than is provided by the Keyboard

controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause

the nALT_RST signal to pulse active (low) for a minimum of 1 µs after a delay of

500 ns. Before another nALT_RST pulse can be generated, this bit must be written

back to a 0.

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