LPC47M192 datasheet(110/228 Pages) SMSC

110 / 228 page

SMSC DS – LPC47M192

Page 110

Rev. 03/30/05

DATASHEET

nGATEA20

8042

P21

ALT_A20

System

nA20M

Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control. This signal

is AND’ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software

means of resetting the CPU. This provides a faster means of reset than is provided by the keyboard controller.

Writing a 1 to bit 0 in the Port 92 Register causes this signal to pulse low for a minimum of 6µs, after a delay of a

minimum of 14µs. Before another nALT_RST pulse can be generated, bit 0 must be set to 0 either by a system reset

of a write to Port 92. Upon reset, this signal is driven inactive high (bit 0 in the Port 92 Register is set to 0).

If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is set to 1, then a pulse is generated by writing a 1 to bit 0 of the Port

92 Register and this pulse is AND’ed with the pulse generated from the 8042. This pulse is output on pin KRESET

and its polarity is controlled by the GPI/O polarity configuration.

8042

P92

Pulse

Gen

KBDRS

KRST_GA2

Bit 2

Bit 0

P20

KRST

nALT RST

6us

14us

6us

14us

Note: When Port 92 is

writes are ignored and

return undefined

Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode compatible

software. This signal is externally OR’ed with the A20GATE signal from the keyboard controller and CPURST to

control the nA20M input of the CPU. Writing a 0 to bit 1 of the Port 92 Register forces ALT_A20 low. ALT_A20 low

drives nA20M to the CPU low, if A20GATE from the keyboard controller is also low. Writing a 1 to bit 1 of the Port 92

from the keyboard controller. Upon reset, this signal is driven low.

LPC47M192 Datasheet(PDF) 110 Page - SMSC Corporation

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